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AD7656A-1BSTZ-RL Fiches technique(PDF) 9 Page - Analog Devices

No de pièce AD7656A-1BSTZ-RL
Description  250 kSPS, 6-Channel, Simultaneous Sampling, Bipolar, 16-Bit ADC
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
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AD7656A-1BSTZ-RL Fiches technique(HTML) 9 Page - Analog Devices

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Data Sheet
AD7656A-1
Pin No.
Mnemonic
Description1
27
RANGE
Analog Input Range Selection. Logic input. The logic level on this pin determines the input range of
the analog input channels. When this pin is Logic 1 at the falling edge of BUSY, the range for the
next conversion is ±2 × VREF. When this pin is Logic 0 at the falling edge of BUSY, the range for the
next conversion is ±4 × VREF. In hardware select mode, the RANGE pin is checked on the falling edge
of BUSY. In software mode (H/S SEL = 1), the RANGE pin can be tied to DGND, and the input range is
determined by the RNGA, RNGB, and RNGC bits in the control register (see Table 9).
28
RESET
Reset Input. When set to logic high, this pin resets the AD7656A-1. In software mode, the current
conversion is aborted, and the internal register is set to all 0s. In hardware mode, the AD7656A-1 is
configured depending on the logic levels on the hardware select pins. In all modes, the AD7656A-1
should receive a RESET pulse after power-up. The RESET high pulse should be typically 100 ns wide.
The CONVST x pin may be held high during the RESET pulse. However, if the CONVST x pin is held low
during the RESET pulse, after the RESET pulse, the AD7656A-1 needs to receive a complete CONVST x
pulse to initiate the first conversion; this consists of a high-to-low CONVST x edge followed by a low-
to-high CONVST x edge. In hardware mode, the user can initiate a RESET pulse between conversion
cycles, that is, a 100 ns RESET pulse can be applied to the device after BUSY has transitioned from high
to low and the data has been read. The RESET can then be issued prior to the next complete CONVST x
pulse. Ensure that in such a case, RESET has returned to logic low prior to the next complete CONVST x
pulse.
29
W/B
Word/Byte Input. When this pin is logic low, data can be transferred to and from the AD7656A-1 using
the parallel data lines DB15 to DB0. When this pin is logic high and the parallel interface is selected,
byte mode is enabled. In this mode, data is transferred using the DB15 to DB8 data lines, and DB7
functions as HBEN. To obtain the 16-bit conversion result, 2-byte reads are required. When the serial
interface is selected, tie this pin to DGND.
30
VSS
Negative Power Supply Voltage. This is the negative supply voltage for the analog input section.
31
VDD
Positive Power Supply Voltage. This is the positive supply voltage for the analog input section.
32, 37, 38, 43,
44, 49, 52, 53,
55, 57, 59
AGND
Analog Ground. This pin is the ground reference point for all analog circuitry on the AD7656A-1. Refer
all analog input signals and external reference signals to this pin. Connect all AGND pins to the
AGND plane of the system. The AGND and DGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.
33, 36, 39,
42, 45, 48
V1 to V6
Analog Input 1 to Analog Input 6. These pins are single-ended analog inputs. In hardware mode,
the analog input range of these channels is determined by the RANGE pin. In software mode, it is
determined by the RNGC to RNGA bits of the control register (see Table 9).
34, 35, 40,
41, 46, 47,
50, 60
AVCC
Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC cores. The AVCC and
DVCC voltages should ideally be at the same potential and must not be more than 0.3 V apart, even
on a transient basis.
51
REFIN/REFOUT
Reference Input/Reference Output. The on-chip reference is available via this pin. Alternatively, the
internal reference can be disabled, and an external reference can be applied to this input. See the
Internal/External Reference section. When the internal reference is enabled, decouple this pin using
at least a 1 µF decoupling capacitor.
54, 56, 58
REFCAPA, REFCAPB,
REFCAPC
Reference Capacitor A, Reference Capacitor B, and Reference Capacitor C. Decoupling capacitors are
connected to these pins to decouple the reference buffer for each ADC pair. Decouple each REFCAP x pin
to AGND using a 1 µF capacitor.
61
SER/PAR SEL
Serial/Parallel Selection Input. When this pin is low, the parallel interface is selected. When this pin is high,
the serial interface is selected. When the serial interface is selected, DB10 to DB8 function as DOUT C to
DOUT A, DB0 to DB2 function as DOUT x, and DB7 functions as DCEN. When the serial interface is
selected, tie DB15 and DB13 to DB11 to DGND.
62
H/S SEL
Hardware/Software Select Input. Logic input. When H/S SEL = 0, the AD7656A-1 is operated in
hardware select mode, and the ADC pairs to be simultaneously sampled are selected by the
CONVST pins. When H/S SEL = 1, the ADC pairs to be sampled simultaneously are selected by
writing to the control register. When the serial interface is selected, CONVST A is used to initiate
conversions on the selected ADC pairs.
63
WR/REFEN/DIS
Write Data/Reference Enable and Disable. When the H/S SEL pin is high and both CS and WR are
logic low, DB15 to DB8 are used to write data to the internal control register. When the H/S SEL pin is
low, this pin is used to enable or disable the internal reference. When H/S SEL = 0 and REFEN/DIS = 0, the
internal reference is disabled and an external reference should be applied to the REFIN/REFOUT pin.
When H/S SEL = 0 and REFEN/DIS = 1, the internal reference is enabled and the REFIN/REFOUT pin
should be decoupled. See the Internal/External Reference section.
1
Multifunction pin names may be referenced by their relevant function only.
Rev. 0 | Page 9 of 28


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