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ADC12041CIMSA Fiches technique(PDF) 6 Page - National Semiconductor (TI) |
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ADC12041CIMSA Fiches technique(HTML) 6 Page - National Semiconductor (TI) |
6 / 28 page Digital Logic Input/Output Characteristics (Continued) The following specifications apply to the ADC12041 for V A+=VD+ = 5V, VREF+ = 4.096V, VREF− = 0.0V, 12-bit + sign con- version mode, f CLK = 12.0 MHz, RS =25Ω, source impedance for VREF+ and VREF− ≤ 1Ω, fully differential input with fixed 2.048V common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T A =TJ =T MIN to TMAX; all other limits TA =TJ = 25˚C Symbol Parameter Conditions Typical Limits Unit (Note 10) (Note 11) (Limit) V OL Logic Low Output Voltage V A+=VD+ = 4.5V 0.4 0.4 V (max) I OUT = 1.6 mA I OFF TRI-STATE Output Leakage Current V OUT =0V ±2.0 µA (max) V OUT =5V C IN D12–D0 Input Capacitance 10 pF Converter AC Characteristics The following specifications apply to the ADC12041 for V S+=VD+ = 5V, VREF+ = 4.096V, VREF− = 0.0V, 12-bit + sign con- version mode, f CLK = 12.0 MHz, RS =25Ω, source impedance for VREF+ and VREF− ≤ 1Ω, fully differential input with fixed 2.048V common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T A =TJ =T MIN to TMAX; all other limits TA =TJ = 25˚C Symbol Parameter Conditions Typical Limits Unit (Note 10) (Note 11) (Limit) t Z Auto Zero Time 78 78 clks + 120 ns clks (max) t CAL Full Calibration Time 4946 4946 clks + 120 ns clks (max) CLK Duty Cycle 50 % 40 % (min) 60 % (max) t CONV Conversion Time Sync-Out Mode 44 44 clks (max) t AcqSYNCOUT Acquisition Time Minimum for 13 Bits 9 9 clks + 120 ns clks (max) (Programmable) Maximum for 13 Bits 79 79 clks + 120 ns clks (max) Digital Timing Characteristics The following specifications apply to the ADC12041, 13-bit data bus width, V A+=VD+ = 5V, fCLK = 12 MHz, tf = 3 ns and CL = 50 pF on data I/O lines Symbol Parameter Conditions Typical Limits Unit (Note 10) (Note 11) (Limit) t TPR Throughput Rate Sync-Out Mode (SYNC Bit = “0”) 9 Clock Cycles of Acquisition Time 222 kHz t CSWR Falling Edge of CS 0ns to Falling Edge of WR t WRCS Active Edge of WR 0ns to Rising Edge of CS t WR WR Pulse Width 20 30 ns (min) t WRSETFalling Write Setup Time WMODE = “1” 20 ns (min) t WRHOLDFalling Write Hold Time WMODE = “1” 5 ns (min) t WRSETRising Write Setup Time WMODE = “0” 20 ns (min) t WRHOLDRising Write Hold Time WMODE = “0” 5 ns (min) t CSRD Falling Edge of CS to Falling Edge of RD 0ns t RDCS Rising Edge of RD 0ns to Rising Edge of CS t RDDATA Falling Edge of RD to Valid Data 8-Bit Mode (BW Bit = “0”) 40 58 ns (max) t RDDATA Falling Edge of RD to Valid Data 13-Bit Mode (BW Bit = “1”) 26 44 ns (max) t RDHOLD Read Hold Time 23 32 ns (max) www.national.com 6 |
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