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SM320VC33GNMM150 Fiches technique(PDF) 6 Page - Texas Instruments |
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SM320VC33GNMM150 Fiches technique(HTML) 6 Page - Texas Instruments |
6 / 53 page SM320VC33, SMJ320VC33 SGUS034F – FEBRUARY 2001 – REVISED JUNE 2015 www.ti.com Pin Functions (continued) PIN CONDITIONS WHEN TYPE(1) DESCRIPTION SIGNAL IS Z TYPE(2) NAME QTY TCLK1 1 I/O/Z Timer clock 1. As an input, TCLK1 is used by timer 1 to count external pulses. As S R an output, TCLK1 outputs pulses generated by timer 1. SUPPLY AND OSCILLATOR SIGNALS H1 1 O/Z External H1 clock S H3 1 O/Z External H3 clock S CVDD 8 I +VDD. Dedicated 1.8-V power supply for the core CPU. All must be connected to a common supply plane.(3) DVDD 16 I +VDD. Dedicated 3.3-V power supply for the I/O pins. All must be connected to a common supply plane.(3) VSS 18 I Ground. All grounds must be connected to a common ground plane. PLLVDD 1 I Internally isolated PLL supply. Connect to CVDD (1.8 V) PLLVSS 1 I Internally isolated PLL ground. Connect to VSS EXTCLK 1 I External clock. Logic level compatible clock input. If the XIN/XOUT oscillator is used, tie this pin to ground. XOUT 1 O Clock out. Output from the internal-crystal oscillator. If a crystal is not used, leave XOUT unconnected. XIN 1 I Clock in. Internal-oscillator input from a crystal. If EXTCLK is used, tie this pin to ground. CLKMD0, 2 I Clock mode select pins CLKMD1 RSV0 to 2 I Reserved. Use individual pullups to DVDD. RSV1 JTAG EMULATION EMU1 to 2 I/O Emulation pins 0 and 1, use individual pullups to DVDD EMU0 TDI 1 I Test data input TDO 1 O Test data output TCK 1 I Test clock TMS 1 I Test mode select TRST 1 I Test reset (3) Recommended decoupling. Four 0.1 μF for CVDD and eight 0.1 μF for DVDD. 6 Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: SM320VC33 SMJ320VC33 |
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