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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AM3871CCYE100 Fiches technique(PDF) 10 Page - Texas Instruments |
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AM3871CCYE100 Fiches technique(HTML) 10 Page - Texas Instruments |
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10 / 358 page  AM3874, AM3871 SPRS695D – SEPTEMBER 2011 – REVISED JANUARY 2016 www.ti.com • Jazelle RCT Acceleration • CP14 Debug Coprocessor • CP15 System Control Coprocessor • NEON™ 64-/128-bit Hybrid SIMD Engine for Multimedia • Enhanced VFPv3 Floating-Point Coprocessor • Enhanced Memory Management Unit (MMU) • Separate Level-1 Instruction and Data Caches • Integrated Level-2 Cache • 128-bit Interconnector-to-System Memories and Peripherals • Embedded Trace Module (ETM). 3.4.2 Embedded Trace Module (ETM) To support real-time trace, the ARM Cortex-A8 processor provides an interface to enable connection of an embedded trace module (ETM). The ETM consists of two parts: • The Trace port which provides real-time trace capability for the ARM Cortex-A8. • Triggering facilities that provide trigger resources, which include address and data comparators, counter, and sequencers. The ARM Cortex-A8 trace port is not pinned out and is, instead, only connected to the system-level Embedded Trace Buffer (ETB). The ETB has a 32KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace data. For more details on the ETM, see Section 9.5.2, Trace. 3.4.3 ARM Cortex-A8 Interrupt Controller (AINTC) The ARM Cortex-A8 subsystem contains an interrupt controller (AINTC) that prioritizes all service requests from the system peripherals and generates either IRQ or FIQ to the ARM Cortex-A8 processor. For more details on the AINTC, see Section 8.5.1, ARM Cortex-A8 Interrupts. Note: For General-Purpose devices, the AINTC does not support the generation of FIQs to the ARM processor. 3.4.4 ARM Cortex-A8 PLL (PLL_ARM) The ARM Cortex-A8 subsystem contains an embedded PLL Controller (PLL_ARM) for generating the subsystem’s clocks from the DEV Clock input. For more details on the PLL_ARM, see Section 8.4, Clocking. 3.4.5 ARM MPU Interconnect The ARM Cortex-A8 processor is connected through the arbiter to both an L3 interconnect port and a DMM port. The DMM port is 128 bits wide and provides the ARM Cortex-A8 direct access to the DDR memories, while the L3 interconnect port is 64 bits wide and provides access to the remaining device modules. 10 Device Overview Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM3874 AM3871 |
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Description similaire - AM3871CCYE100 |
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