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SP6123 Datasheet(Fiches technique) 5 Page - Sipex Corporation

Numéro de pièce SP6123
Description  Low Voltage, Synchronous Step-Down PWM Controller Ideal for 2A to 10A, Small Footprint, DC-DC Power Converters
Télécharger  18 Pages
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Fabricant  SIPEX [Sipex Corporation]
Site Internet  http://www.sipex.com
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5
Date: 5/25/04
SP6123 Low Voltage, Synchronous Step Down PWM Controller
© Copyright 2004 Sipex Corporation
A low power sleep mode can be invoked in the
SP6123 by externally forcing the COMP pin
below 0.3V. Quiescent supply current in sleep
mode is typically less than 30
µA. An internal
5
µA pull-up current at the COMP pin brings the
SP6123 out of shutdown mode.
An internal 0.8V 1.5% reference allows output
voltage adjustment for low voltage applications.
The SP6123 also includes an accurate under-
voltage lockout that shuts down the controller
when the input voltage falls below 2.7V. Output
overvoltage protection is achieved by turning
off the high side switch and turning on the low
side N-channel MOSFET 100% of the time.
Enable
Low quiescent mode or “Sleep Mode” is initi-
ated by pulling the COMP pin below 0.3V with
an external open-drain or open-collector tran-
sistor. Supply current is reduced to 30
µA (typi-
cal) in shutdown. On power-up, assuming that
VCC has exceeded the UVLO start threshold
(2.8V), an internal 5
µA pull-up current at the
COMP pin brings the SP6123 out of shutdown
mode and ensures start-up. During normal oper-
ating conditions and in absence of a fault, an
internal clamp prevents the COMP pin from
swinging below 0.6V. This guarantees that dur-
ing mild transient conditions, due either to line
or load variations, the SP6123 does not enter
shutdown unless it is externally activated.
During Sleep Mode, the high side and low side
MOSFETS are turned off and the internal soft
start voltage is held low.
UVLO
Assuming that there is not shutdown condition
present, then the voltage on the VCC pin deter-
mines operation of the SP6123. As VCC rises,
the UVLO block monitors VCC and keeps the
high side and low side MOSFETS off and the
internal SS voltage low until VCC reaches 2.8V.
If no faults are present, the SP6123 will initiate
a soft start when VCC exceeds 2.8 V.
Hysteresis (about 100mV) in the UVLO com-
parator provides noise immunity at start-up.
Soft Start
Soft start is required on step-down controllers to
prevent excess inrush current through the power
train during start-up. Typically this is managed
by sourcing a controlled current into a timing
capacitor and then using the voltage across this
capacitor to slowly ramp up either the error amp
reference or the error amp output (COMP). The
control loop creates narrow width driver pulses
while the output voltage is low and allows these
pulses to increase to their steady-state duty
cycle as the output voltage increases to its regu-
lated value. As a result of controlling the induc-
tor volt*second product during startup, inrush
current is also controlled.
In the SP6123 the duration of the soft-start is
controlled by an internal timing circuit that
provides a 0.27V/ms slew-rate, which is used
during startup and overcurrent to set the hiccup
time. The SP6123 implements soft-start by ramp-
ing up the error amplifier reference voltage
providing a controlled slew-rate of the output
voltage, thereby preventing overshoot and in-
rush current at power up.
The presence of the output capacitor creates
extra current draw during startup. Simply stated,
dVOUT/dt requires an average sustained current
in the output capacitor and this current must be
considered while calculating peak inrush cur-
rent and over current thresholds. An approxi-
mate expression to determine the excess inrush
current due to the dVOUT/dt of the output capaci-
tor COUT is:
Iinrush = COUT x SSS x
VOUT
0.8V
Where,
SSS = Softstart slew rate, 0.6V/ms for SP6123A
and 0.3V/ms for SP6123.
As the figure shows, the SS voltage controls a
variety of signals. First, provided all the exter-
nal fault conditions are removed, an internal
5
µA pull-up at the COMP pin brings the SP6123
out of shutdown mode. The internal timing
circuit is then activated and controls the ramp-
up of the error amp reference voltage. The
COMP pin is pulled to 0.7V by the internal
OPERATION: continued
OPERATION




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