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SP6123 Datasheet(Fiches technique) 3 Page - Sipex Corporation

Numéro de pièce SP6123
Description  Low Voltage, Synchronous Step-Down PWM Controller Ideal for 2A to 10A, Small Footprint, DC-DC Power Converters
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Fabricant  SIPEX [Sipex Corporation]
Site Internet  http://www.sipex.com
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Date: 5/25/04
SP6123 Low Voltage, Synchronous Step Down PWM Controller
© Copyright 2004 Sipex Corporation
PIN DESCRIPTION
PIN N0. PIN NAME DESCRIPTION
1GL
High current driver output for the low side MOSFET switch. It is always low if GH is high.
GL swings from GND to VCC.
2VCC
Positive input supply for the control circuitry and the low side gate driver. Properly bypass
this pin to GND with a low ESL/ESR ceramic capacitor.
3
GND
Ground pin. Both power and control circuitry of the IC is referenced to this pin.
4
COMP
Output of the Error Amplifier. It is internally connected to the non-inverting input of the
PWM comparator. A lead-lag network is typically connected to the COMP pinto compen-
sate the feedback loop in order to optimize the dynamic performance of the voltage mode
control loop. Sleep mode can be invoked by pulling the COMP pin below 0.3V with an
external open-drain or open-collector transistor. Supply current is reduced to 30µA (typical)
in shutdown. An internal 5µA pull-up ensures start-up.
5VFB
Feedback Voltage Pin. It is the inverting input of the Error Amplifier and serves as the
output voltage feedback point for the Buck converter. The output voltage is sensed and
can be adjusted through an external resistor divider.
6
SWN
Lower supply rail for the GH high-side gate driver. It also connects to the Current Limit
comparator. Connect this pin to the switching node at the junction between the two
external power MOSFET transistors. This pin monitors the voltage drop across the RDS(ON)
of the high side N-channel MOSFET while it is conducting. When this drop exceeds the
internal 200mV threshold, the overcurrent comparator sets the fault latch and terminates
the output pulses. The controller stops switching and goes through a hiccup sequence. This
prevents excessive power dissipation in the external power MOSFETS during an overload
condition. An internal delay circuit prevents that very short and mild overload conditions,
that could occur during a load transient, from activating the current limit circuit.
7GH
High current driver output for the high side MOSFET switch. It is always low if GL is high or
during a fault. GH swings from SWN to BST.
8
BST
High side driver supply pin. Connect BST to the external boost diode and capacitor as
shown in the application schematic of page #1. Voltage between BST and SWN should
not exceed 5.5V.
Unless otherwise specified: 0°C < TA < 70°C, 3.0V < VCC < 5.5V, CCOMP = 22nF, CGH = CGL = 3.3nF, VFB = 0.8V,
SWN = GND=0V, typical value for design guideline only.
PARAMETER
MIN TYP
MAX
UNITS
CONDITIONS
GATE DRIVERS
GH Rise Time
110
ns
VCC > 4.5V
GH Fall Time
110
ns
VCC > 4.5V
GL Rise Time
110
ns
VCC > 4.5V
GL Fall Time
110
ns
VCC > 4.5V
GH to GL Non-Overlap Time
100
ns
VCC > 4.5V
GL to GH Non-Overlap Time
100
ns
VCC > 4.5V
ELECTRICAL CHARACTERISTICS




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Datasheet Download



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