AD9993BBCZ datasheet(2/56 Pages) AD

No de pièce	AD9993BBCZ

Description	Integrated Mixed-Signal Front End (MxFE)

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AD9993

Data Sheet

Rev. A | Page 2 of 56

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

AC Specifications.......................................................................... 5

Digital Specifications ................................................................... 5

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ........................................... 11

Receiver ADC Performance...................................................... 11

Transmitter DAC Performance................................................. 13

Terminology .................................................................................... 15

Theory of Operation ...................................................................... 16

Product Description................................................................... 16

SPI Port ........................................................................................ 16

SPI Configuration Programming............................................. 17

Register Update Transfer Method ............................................ 17

ADC Register Update Indexing................................................ 17

ADCs............................................................................................ 17

ADC Architecture ...................................................................... 17

ADC Section Programming...................................................... 17

Analog Input Considerations.................................................... 17

DACs ............................................................................................ 18

DAC Transfer Function ............................................................. 18

DAC Output Compliance Voltage Range and AC

Performance ................................................................................ 18

DAC Voltage Reference ............................................................. 19

DAC Gain Setting....................................................................... 19

DAC Datapath Format Selection.............................................. 19

DAC Test Tone Generator DDS................................................ 19

Clocking....................................................................................... 20

On-Chip PLL Clock Multiplier ................................................ 20

Selecting Clocking Options....................................................... 21

ADC Datapath and DAC Datapath FIFOs ............................. 21

LVDS Interfaces .......................................................................... 21

LVDS Interface Timing.............................................................. 22

LVDS Lane Testing Using PRBS............................................... 23

Power Mode Programming....................................................... 23

Interrupt Request Operation .................................................... 23

Temperature Sensor ................................................................... 23

Start-Up Register Sequences ......................................................... 25

Power-Up Routine When Using the On-Chip Clock

Synthesizer .................................................................................. 25

Power-Up Routine When Using External Clock ................... 25

Applications Information .............................................................. 27

Direct Conversion Radio Application ..................................... 27

Register Map ................................................................................... 28

Register Descriptions ..................................................................... 30

SPI Configuration Register ....................................................... 30

Chip ID Register......................................................................... 30

Chip Grade Register................................................................... 31

Device Index Register ................................................................ 31

Power Mode Control Register .................................................. 32

Align ADC LVDS Clocks, ADC FIFO, DAC FIFO Register 32

Strobe Lane Control Register.................................................... 33

Output Mode Register ............................................................... 33

LVDS Tx Control Register ........................................................ 34

VREF Control Register ................................................................. 34

PRBS Generator Control Register............................................ 35

8-Bit Seed MSB of PRBS Generator for Lane 0 Register....... 35

8-Bit Seed MSB of PRBS Generator for Lane 1 Register....... 36

8-Bit Seed MSB of PRBS Generator for Lane 2 Register....... 36

8-Bit Seed MSB of PRBS Generator for Lane 3 Register....... 36

Synthesizer Status Register........................................................ 37

Loop Filter Control Signals Register........................................ 37

Loop Filter Control Signals Register........................................ 38

Integer Value of Synthesizer Divider Register ........................ 39

Synthesizer Control Register .................................................... 39

Clock Generator Control Register ........................................... 39

CLKGEN Control Register ....................................................... 40

DAC LVDS Rx Control Register .............................................. 40

DAC LVDS Current Bias Control Register ............................. 41

DAC Cores Control Register .................................................... 42

DAC Datapath Format Control Register ................................ 42

Numéro de pièce similaire - AD9993BBCZ

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Analog Devices	AD9993BBCZ	2Mb / 57P	Integrated Mixed-Signal Front End
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