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AD6679 Fiches technique(PDF) 1 Page - Analog Devices

No de pièce AD6679
Description  135 MHz BW IF Diversity Receiver
Download  81 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD6679 Fiches technique(HTML) 1 Page - Analog Devices

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135 MHz BW IF Diversity Receiver
Data Sheet
AD6679
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
FEATURES
Parallel LVDS (DDR) outputs
In-band SFDR = 82 dBFS at 340 MHz (500 MSPS)
In-band SNR = 67.8 dBFS at 340 MHz (500 MSPS)
1.1W total power per channel at 500 MSPS (default settings)
Noise density = −153 dBFS/Hz at 500 MSPS
1.25 V, 2.50 V, and 3.3 V dc supply operation
Flexible input range
1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)
95 dB channel isolation/crosstalk
Amplitude detect bits for efficient automatic gain control
(AGC) implementation
Noise shaping requantizer (NSR) option for main receiver
function
Variable dynamic range (VDR) option for digital
predistortion (DPD) function
2 integrated wideband digital processors per channel
12-bit numerically controlled oscillator (NCO), up to
4 cascaded half-band filters
Differential clock inputs
Integer clock divide by 1, 2, 4, or 8
Energy saving power-down modes
Small signal dither
APPLICATIONS
Diversity multiband, multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
GENERAL DESCRIPTION
The AD6679 is a 135 MHz bandwidth mixed-signal intermediate
frequency (IF) receiver. It consists of two, 14-bit, 500 MSPS
analog-to-digital converters (ADCs) and various digital signal
processing blocks consisting of four wideband DDCs, an NSR,
and VDR monitoring. It has an on-chip buffer and a sample-and-
hold circuit designed for low power, small size, and ease of use.
This product is designed to support communications applications
capable of sampling wide bandwidth analog signals of up to 2 GHz.
The AD6679 is optimized for wide input bandwidth, high sampling
rates, excellent linearity, and low power in a small package.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations.
FUNCTIONAL BLOCK DIAGRAM
VIN+A
VIN–A
CLK+
CLK–
AVDD1
(1.25V)
AVDD2
(2.50V)
DRVDD
(1.25V)
SDIO
SCLK
CSB
AGND
AD6679
DVDD
(1.25V)
DRGND
SYNC±
CLOCK
GENERATION
AND ADJUST
SPI CONTROL
PDWN/STBY
SPIVDD
(1.22V TO 3.4V)
FD_A
FD_B
FAST
DETECT
BUFFER
V_1P0
SIGNAL
MONITOR
LVDS
OUTPUTS
LVDS
OUTPUT
STAGING
DATA
ROUTER
MUX
VIN+B
VIN–B
SIGNAL
MONITOR
FAST
DETECT
BUFFER
DGND
AVDD3
(3.3V)
SIGNAL PROCESSING
D0±
16
D1±
D2±
D3±
D4±
D5±
D6±
D7±
D8±
D9±
D10±
D11±
D12±
D13±
DCO±
STATUS±
ADC
ADC
÷2
÷4
÷8
DIGITAL DOWN-
CONVERSION
(×4)
NOISE SHAPING
REQUANTIZER
(×2)
VARIABLE
DYNAMIC RANGE
(×2)
Figure 1.


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