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CD4042BC Fiches technique(PDF) 1 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No de pièce CD4042BC
Description  Quad Clocked D Latch
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Fabricant  NSC [National Semiconductor (TI)]
Site Internet  http://www.national.com
Logo NSC - National Semiconductor (TI)

CD4042BC Fiches technique(HTML) 1 Page - National Semiconductor (TI)

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TLF5966
March 1988
CD4042BMCD4042BC Quad Clocked D Latch
General Description
The CD4042BMCD4042BC quad clocked ‘‘D’’ latch is a
monolithic complementary MOS (CMOS) integrated circuit
constructed with P- and N-channel enhancement mode
transistors The outputs Q and Q either latch or follow the
data input depending on the clock level which is pro-
grammed by the polarity input For polarity e 0 the informa-
tion present at the data input is transferred to Q and Q
during 0 clock level and for polarity e 1 the transfer occurs
during the 1 clock level When a clock transition occurs
(positive for polarity e 0 and negative for polarity e 1) the
information present at the input during the clock transition is
retained at the outputs until an opposite clock transition oc-
curs
Features
Y
Wide supply voltage range
30V to 15V
Y
High noise immunity
045 VDD (typ)
Y
Low power TTL
Fan out of 2 driving 74L
compatibility
or 1 driving 74LS
Y
Clock polarity control
Y
Fully buffered data inputs
Y
Q and Q outputs
Connection Diagram
Dual-In-Line Package
TLF5966 – 1
Top View
Truth Table
Clock
Polarity
Q
00
D
L
0
Latch
11
D
K
1
Latch
Order Number CD4042B
Logic Diagrams
TLF5966 – 2
TLF5966 – 3
TLF5966 – 4
C1995 National Semiconductor Corporation
RRD-B30M105Printed in U S A


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