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TS81001-QFNR Fiches technique(PDF) 6 Page - Semtech Corporation

No de pièce TS81001-QFNR
Description  High Efficiency Receiver Controller for Wireless Power Systems
Download  16 Pages
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Fabricant  SEMTECH [Semtech Corporation]
Site Internet  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

TS81001-QFNR Fiches technique(HTML) 6 Page - Semtech Corporation

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TS81001
Final Datasheet
Rev 1.2
June 2, 2015
www.semtech.com
6 of 16
Semtech
I2C
I2C Signal Pins
ALERT pin (GPIO pin) - optional:
Œ
Driven high when an event is active in the internal STATUS register
Œ
Driven low when all the internal events are cleared
Note: The ALERT pin is provided to help with I2C communication, i.e. to signal events to the EC so the EC can interrogate the TS8100x via I2C.
The use of the ALERT pin is not mandatory in the application.
SCL_TXD pin:
Œ
Clock pin for the I2C interface.
Œ
True open-drain. Needs external pull-ups.
SDA_RXD pin:
Œ
Data pin for the I2C interface.
Œ
True open-drain. Needs external pull-ups.
I2C Protocol
The TS81001 Wireless Power Receiver acts as an I2C slave peripheral to allow communication with an application microcontroller.
The slave address (7 bit) is 0x49. The Embedded Controller is an I2C master and initiates every data transfer.
The TS81001 implements a set of registers available from the I2C bus. It also implements a set of API functions that receive
parameters and return values using the I2C bus. Four transfer types are possible:
Write Register
Read Register
Run API Function
Read API Function Return Buffer
Write Register Operations
Description
START
Start of the I2C transfer
M[S
Slave Address (7 bits)
0 (1 bit) Slave ACK
Slave address + R/nW bit (0x92 as 8-bit).
M[S
Register n address (8 bits)
Slave ACK
Address of the first register.
M[S
Register n Data (8 bits)
Slave ACK
Write the first register.
M[S
Register n+1 Data (8 bits)
Slave ACK
Optionally write the following registers.
...
M[S
Register n+k Data (8 bits)
Slave ACK
STOP
Stop of the I2C transfer.


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