C1

1D

R

C1

1D

R

Q

Q

A

B

C1

1D

R

C1

1D

R

Q

Q

C

D

C1

1D

R

C1

1D

R

Q

Q

E

F

C1

1D

R

C1

1D

R

Q

Q

G

H

3

4

5

6

10

11

12

13

8

1

2

9

CLK

A

B

CLR

Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages.

SN54LV164A, SN74LV164A

www.ti.com

SCLS403I – APRIL 1998 – REVISED MARCH 2015

8 Detailed Description

8.1 Overview

These devices feature NAND-gated serial (A and B) inputs and an asynchronous clear (CLR) input. The gated

serial inputs permit complete control over incoming data, as a low at either input inhibits entry of the new data

and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input,

which then determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is

high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level

transition of the clock (CLK) input.

8.2 Functional Block Diagram

Figure 5. Logic Diagram (Positive Logic)

8.3 Feature Description

The wide operating range allows the device to be used in a variety of systems that use different logic levels. The

low propagation delay allows fast switching and higher speeds of operation. In addition, the low ground bounce

stabilizes the performance of non-switching outputs while another output is switching.

8.4 Device Functional Modes

INPUTS

OUTPUTS

CLR

CLK

A

B

...

L

X

X

X

L

L

L

H

L

X

X

H

↑

H

H

H

H

↑

L

X

L

H

↑

X

L

L

(1)

indicated steady-state input conditions were established.

(2)

of the clock: indicates a 1-bit shift.

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SN74LV164A