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STHVDAC-253MTG Fiches technique(PDF) 8 Page - STMicroelectronics |
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STHVDAC-253MTG Fiches technique(HTML) 8 Page - STMicroelectronics |
8 / 28 page Theory of operation STHVDAC-253MTG 8/28 DocID027917 Rev 4 3.1.2 DAC operation in turbo mode -- glide_enable = 0b, turbo_mode = 1b A specific turbo mode is implemented in the STHVDAC-253MTG to ensure a fast system settling time. In this mode, the DAC voltage outputs are optimized to minimize the settling time on the output capacitor load (Vout_Cload, see Figure 3). Once enabled, the output voltage on the output capacitor reaches its final value within 55µs typical. In turbo mode, STHVDAC-253MTG has been optimized to support up to 4 different output RC loads, as defined in Table 6. The RC loads can be selected for each output independently, by controlling PTIC_selection bits in registers#9 to 11. Typical timing diagram in turbo mode is shown on Figure 4. 3.1.3 DAC operation in glide mode - glide_enable = 1b, turbo_mode = x Glide mode has been implemented to smooth DAC output voltage transition, and to minimize the impact of tunable capacitor changes on RF system performance (especially to meet 3GPP phase discontinuity requirements). In this mode, the DAC output voltage transitions from old to new voltage value, in a period of time equal to the glide_delay defined as : Glide_delay = glide_step_delay * 256 (programmable from 512 µs up to 16.84 ms) glide_step_delay defined in registers#1 and 5 as per Table 11. Typical timing diagram in glide mode is shown on Figure 4. Table 6. Supported output RC loads (turbo mode only) PTIC_selection bits Rload Cload 00 12 kΩ 2.7 nF 01 17 kΩ 2.7 nF 10 22 kΩ 2.7 nF 11 27 kΩ 2.7 nF |
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