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TCAN334GDR Fiches technique(PDF) 8 Page - Texas Instruments

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No de pièce TCAN334GDR
Description  CAN Transceivers
Download  39 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

TCAN334GDR Fiches technique(HTML) 8 Page - Texas Instruments

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8
TCAN330, TCAN332, TCAN334, TCAN337
TCAN330G, TCAN332G, TCAN334G, TCAN337G
SLLSEQ7A – DECEMBER 2015 – REVISED JANUARY 2016
www.ti.com
Product Folder Links: TCAN330 TCAN332 TCAN334 TCAN337 TCAN330G TCAN332G TCAN334G TCAN337G
Submit Documentation Feedback
Copyright © 2015–2016, Texas Instruments Incorporated
(1)
The TXD dominant time out (tTXD_DTO) disables the driver of the transceiver once the TXD has been dominant longer than tTXD_DTO,
which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit
dominant again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it
limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst
case, where five successive dominant bits are followed immediately by an error frame. This, along with the tTXD_DTO minimum, limits the
minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/ tTXD_DTO = 11 bits / 1.2 ms = 9.2 kbps.
(2)
The RXD timeout (tRXD_DTO) disables the RXD output in the case that the bus has been dominant longer than tRXD_DTO, which releases
RXD pin to the recessive state (high), thus preventing a dominant bus failure from permanently keeping the RXD pin low. The RXD pin
will automatically resume normal operation once the bus has been returned to a recessive state. While this protects the protocol
controller from a permanent dominant state, it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven
successive dominant bits (on RXD) for the worst case, where five successive dominant bits are followed immediately by an error frame.
This, along with the tRXD_DTO minimum, limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11 /
tRXD_DTO = 11 bits / 1.6 ms = 6.9 kbps.
8.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DEVICE SWITCHING CHARACTERISTICS
tPROP(LOOP)
Total loop delay, driver input (TXD) to
receiver output (RXD), recessive to
dominant and dominant to recessive
See Figure 23, S, STB and SHDN = 0 V,
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF
100
135
ns
tPROP(LOOP)
Total Loop delay in highly loaded
network
See Figure 23, S, STB and SHDN = 0 V,
RL = 120 Ω, CL = 200 pF,
CL(RXD) = 15 pF
120
180
ns
tBUS_SYM_2
2 Mbps transmitted recessive bit width
See Figure 24, S or STB = 0 V, RL = 60
Ω, CL = 100 pF, CL(RXD) = 15 pF,
tBIT = 500 ns
TCAN330G, TCAN332G, TCAN334G
and TCAN337G only
435
530
ns
tREC_SYM_2
2 Mbps received recessive bit width
400
550
ns
ΔtSYM_2
2 Mbps receiver timing symmetry
(tREC_SYM_2 - tBUS_SYM_2)
–65
40
ns
tBUS_SYM_5
5 Mbps transmitted recessive bit width
See Figure 24, S or STB = 0 V, RL = 60
Ω, CL = 100 pF, CL(RXD) = 15 pF,
tBIT = 200 ns
TCAN330G, TCAN332G, TCAN334G
and TCAN337G only
155
210
ns
tREC_SYM_5
5 Mbps received recessive bit width
120
220
ns
ΔtSYM_5
5 Mbps receiver timing symmetry
(tREC_SYM_5 - tBUS_SYM_5)
–45
15
ns
tMODE
Mode change time
See Figure 21 and Figure 22.
RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF
5
10
µs
tUV_RE-ENABLE
Re-enable time after UV event
Time for device to return to normal
operation from UV(VCC) under voltage
event
1000
µs
tWK_FILTER
Bus time to meet Filtered Bus
Requirements for Wake Up Request
See Figure 33, Standby mode.
–12 V < VCM < 12 V
0.5
4
µs
DRIVER SWITCHING CHARACTERISTICS
tpHR
Propagation delay time, HIGH TXD to
Driver Recessive
See Figure 19, S, STB and SHDN = 0 V.
RL = 60 Ω, CL = 100 pF,
25
ns
tpLD
Propagation delay time, LOW TXD to
Driver Dominant
20
tsk(p)
Pulse skew (|tpHR - tpLD|)
5
tr
Differential output signal rise time
17
tf
Differential output signal fall time
9
tTXD_DTO
Driver dominant time out (1)
See Figure 25,
RL = 60 Ω, CL = 100 pF
1.2
2.6
3.8
ms
RECEIVER SWITCHING CHARACTERISTICS
tpRH
Propagation delay time, bus recessive
input to high RXD output
See Figure 20, CL(RXD) = 15 pF CANL =
1.5 V, CANH = 3.5 V
62
ns
tpDL
Propagation delay time, bus dominant
input to RXD low output
56
tr
Output signal rise time (RXD)
7
tf
Output signal fall time (RXD)
6
tRXD_DTO
Receiver dominant time out (2)
See Figure 27, CL(RXD) = 15 pF
1.6
3
5
ms


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