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DAC3482 Fiches technique(PDF) 3 Page - Texas Instruments |
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DAC3482 Fiches technique(HTML) 3 Page - Texas Instruments |
3 / 106 page DAC3482 www.ti.com SLAS748F – MARCH 2011 – REVISED AUGUST 2015 Revision History (continued) • Added clarification on timing requirement acronyms to Multi-Device Synchronization: PLL Enabled with Dual Sync Sources Mode. .................................................................................................................................................................... 59 • Deleted or in Power-Up Sequence description .................................................................................................................... 62 • Changed P = 3 to P = 4 in PLL Configuration to reflect the correct example start-up routine configuration ...................... 62 • Added pin description for both packages ............................................................................................................................. 69 • Changed Config7, bit 3 naming typo ................................................................................................................................... 71 • Changed config10 to config11 and 0x0A to 0x0B in register config11 ................................................................................ 72 • Changed QMC offset registers to QMC correction registers in config16 function .............................................................. 73 • Changed Qfine to fine in config18 function ......................................................................................................................... 73 • Added reference in config26 function .................................................................................................................................. 75 • Added additional operation requirement for SLEEP pin if SLEEP pin is set to logic HIGH before and during device power up and initialization in config27 function ................................................................................................................... 76 • Changed 1.2VDIG to DIGVDD in config27 function ............................................................................................................. 76 • Added pin description for both packages to register config35 description ........................................................................... 79 • Added reference to Digital Input Timing Specifications in register config36 description...................................................... 79 Changes from Revision D (August 2012) to Revision E Page • Changed Power Supply Specification Table under Electrical Specification. This specification depends on the enhanced production test coverage and is specific to devices with certain date code. Refer to Clarifications for DAC3482 Power Supply and Phase-Locked Loop Specification Section for details ........................................................... 14 • Deleted Note (5) in Power Consumption Specification to reflect the latest DAC3482 speed specification. ....................... 14 • Changed DACCLKP/N typical clock swing specification to reflect commonly used LVPECL driver.................................... 15 • Changed DACCLKP/N typical clock swing specification to reflect commonly used LVPECL driver.................................... 15 • Changed DACCLK driver requirement to reflect actual device performance under commonly used LVPECL drivers ....... 15 • Changed Analog Output Specification Table under Electrical Specification. This specification depends on the enhanced production test coverage and is specific to devices with certain date code. Refer to Clarifications for DAC3482 Power Supply and Phase-Locked Loop Specification Section for details ........................................................... 16 • Added Phase-Locked Loop Specification Table under Electrical Specification. This specification depends on the enhanced production test coverage and is specific to devices with certain date code. Refer to Clarifications for DAC3482 Power Supply and Phase-Locked Loop Specification Section for details ........................................................... 16 • Changed Digital Latency Specification for QMC to reflect the actual DAC3482 parameter ................................................ 18 • Changed Digital Latency Specification for Inverse Sinc to reflect the actual DAC3482 parameter ..................................... 18 • Changed syncsel_fifoout(3:0) description to clarify the FIFO read pointer reset capture method and limitation................. 32 • Changed information to Single Sync Source Mode section to clarify the latency limitation of Single Sync Source Mode .. 34 • Added "the effect of bypassing the FIFO" in the Bypass Mode section to clarify the operation of FIFO, LVDS FRAME, and LVDS SYNC in FIFO Bypass Mode................................................................................................................ 34 • Changed PLL Mode section with additional operating recommendations for the DAC3482 on-chip PLL ........................... 36 • Changed Data Pattern Checker section with additional operating recommendations ......................................................... 47 • Added additional requirements for Block Parity section when byte wide input data mode is selected................................ 50 • Changed information to Multi-Device Operation: Single Sync Source Mode section to clarify the latency limitation of Single Sync Source Mode .................................................................................................................................................... 60 • Changed Figure 90 to clarify the latency limitation of Single Sync Source Mode................................................................ 61 • Changed the NCO setting description in the Example Start-up Sequence Section to reflect the example register writes . 63 • Changed pll_vco(6:0) to pll_vco(5:0) to reflect actual bit width in the register..................................................................... 75 • Changed config45, bit12:1 default value to reflect the actual default register value............................................................ 80 • Changed config45, bit0 description to clarify additional DAC3482 behavior........................................................................ 80 Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: DAC3482 |
Numéro de pièce similaire - DAC3482_15 |
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Description similaire - DAC3482_15 |
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