DAC34SH84IZAY datasheet(8/93 Pages) TI1

No de pièce	DAC34SH84IZAY

Description	Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC)

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Fabricant	TI1 [Texas Instruments]

Site Internet	http://www.ti.com

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8 / 93 page

DAC34SH84

SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015

www.ti.com

Electrical Characteristics – DC Specifications (continued)

over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TEMPERATURE COEFFICIENTS

Offset drift

±1

ppm / °C

With external reference

±15

ppm / °C

Gain drift

With internal reference

±30

ppm / °C

Reference voltage drift

±8

ppm / °C

POWER SUPPLY(3)

AVDD, IOVDD, PLLAVDD

3.14

3.3

3.46

V

DIGVDD

1.25

1.3

1.35

V

CLKVDD, DACVDD

1.3

1.35

1.4

V

IOVDD2

1.71

3.3

3.45

V

PSRR

Power-supply rejection ratio

DC tested

±0.25

%FSR / V

POWER CONSUMPTION

I(AVDD)

Analog supply current(4)

135

165

mA

Mode 1

I(DIGVDD)

Digital supply current

885

950

mA

fDAC = 1.5 GSPS, 2× interpolation,

I(DACVDD)

DAC supply current

45

60

mA

mixer on, QMC on, invsinc on,

I(CLKVDD)

Clock supply current

127

145

mA

PLL enabled, 20-mA FS output, IF = 200 MHz

P

Power dissipation

1828

2056

mW

I(AVDD)

Analog supply current(4)

115

mA

Mode 2

I(DIGVDD)

Digital supply current

770

mA

fDAC = 1.47456 GSPS, 2× interpolation,

I(DACVDD)

DAC supply current

40

mA

mixer on, QMC on, invsinc on,

I(CLKVDD)

Clock supply current

95

mA

PLL disabled, 20-mA FS output, IF = 7.3 MHz

P

Power dissipation

1562

mW

I(AVDD)

Analog supply current(4)

115

mA

Mode 3

I(DIGVDD)

Digital supply current

470

mA

fDAC = 737.28 MSPS, 2x interpolation,

I(DACVDD)

DAC supply current

21

mA

mixer on, QMC on, invsinc off,

I(CLKVDD)

Clock supply current

55

mA

PLL disabled, 20-mA FS output, IF = 7.3 MHz

P

Power dissipation

1093

mW

I(AVDD)

Analog supply current(4)

40

mA

Mode 4

I(DIGVDD)

Digital supply current

710

mA

fDAC = 1.47456 GSPS, 2× interpolation,

I(DACVDD)

DAC supply current

mixer on, QMC on, invsinc on,

50

mA

PLL enabled, IF = 7.3 MHz, channels A/B/C/D

I(CLKVDD)

Clock supply current

90

mA

output sleep

P

Power dissipation

1160

mW

I(AVDD)

Analog supply current(4)

28

mA

Mode 5

I(DIGVDD)

Digital supply current

17

mA

Power-down mode: no clock, DAC on sleep

I(DACVDD)

DAC supply current

mode (clock receiver sleep),

0

mA

channels A/B/C/D output sleep, static data

I(CLKVDD)

Clock supply current

20

mA

pattern

P

Power dissipation

142

mW

I(AVDD)

Analog supply current(4)

130

mA

Mode 6

I(DIGVDD)

Digital supply current

570

mA

fDAC = 1 GSPS, 2x interpolation,

I(DACVDD)

DAC supply current

25

mA

mixer off, QMC off, invsinc off,

I(CLKVDD)

Clock supply current

98

mA

PLL enabled, 20-mA FS output, IF = 7.3 MHz

P

Power dissipation

1336

mA

(3)

To ensure power supply accuracy and to account for power supply filter network loss at operating conditions, the use of the ATEST

function in register config27 to check the internal power supply nodes is recommended.

(4)

Includes AVDD, PLLAVDD, and IOVDD

8

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