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STF10LN80K5 Fiches technique(PDF) 4 Page - STMicroelectronics |
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STF10LN80K5 Fiches technique(HTML) 4 Page - STMicroelectronics |
4 / 14 page Electrical characteristics STF10LN80K5 4/14 DocID027751 Rev 3 2 Electrical characteristics TC = 25 °C unless otherwise specified Table 5: On/off-state Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA 800 V IDSS Zero gate voltage drain current VGS = 0 V, VDS = 800 V 1 µA VGS = 0 V, VDS = 800 V TC = 125 °C 50 µA IGSS Gate body leakage current VDS = 0 V, VGS = ±20 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA 3 4 5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 4 A 0.55 0.63 Ω Table 6: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V - 427 - pF Coss Output capacitance - 43 - pF Crss Reverse transfer capacitance - 0.25 - pF Co(tr) (1) Equivalent capacitance time related VDS = 0 to 640 V, VGS = 0 V - 72 - pF Co(er) (2) Equivalent capacitance energy related 27 - pF Rg Intrinsic gate resistance f = 1 MHz , ID= 0 A - 7 - Ω Qg Total gate charge VDD = 640 V, ID = 8 A VGS= 10 V See Figure 16: "Test circuit for gate charge behavior" - 15 - nC Qgs Gate-source charge - 4.2 - nC Qgd Gate-drain charge - 9 - nC Notes: (1) Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS (2) Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS Table 7: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD= 400 V, ID = 4 A, RG = 4.7 Ω VGS = 10 V See Figure 15: "Test circuit for resistive load switching times" and Figure 20: "Switching time waveform" - 11.8 - ns tr Rise time - 10 - ns td(off) Turn-off delay time - 28 - ns tf Fall time - 13 - ns |
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