CDCP1803RTHR datasheet(9/25 Pages) TI1

No de pièce	CDCP1803RTHR

Description	1:3 LVPECL CLOCK BUFFER

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Fabricant	TI1 [Texas Instruments]

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f − Frequency − MHz

3 LVPECL Outputs

(P1) Running

VDD = 3.3 V,

TA = 255C,

50 W to VDD −2 V for LVPECL

G003

CDCP1803

www.ti.com

SCAS727F – NOVEMBER 2003 – REVISED DECEMBER 2013

SUPPLY CURRENT

vs

FREQUENCY

Figure 4.

PACKAGE THERMAL RESISTANCE

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

4-layer JEDEC test board (JESD51-7),

RθJA-1

QFN-24 package thermal resistance(1)

106.6

°C/W

airflow = 0 ft/min

4-layer JEDEC test board (JESD51-7) with four

QFN-24 package thermal resistance

RθJA-2

thermal vias of 22-mil diameter each,

55.4

°C/W

with thermal vias in PCB(1)

airflow = 0 ft/min

(1)

It is recommended to provide four thermal vias to connect the thermal pad of the package effectively with the PCB and ensure a good

heat sink.

Example:

Calculation of the junction-lead temperature with a 4-layer JEDEC test board using four thermal vias:

TChassis = 85°C (temperature of the chassis)

Peffective = Imax × Vmax = 90 mA × 3.6 V = 324 mW (max power consumption inside the package)

θTJunction = θJA-2 × Peffective = 55.45°C/W × 324 mW = 17.97°C

TJunction = θTJunction + TChassis = 17.97°C + 85°C = 103°C (the maximum junction temperature of

Tdie-max = 125°C is not violated)

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