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SL23EP04NZ Fiches technique(PDF) 5 Page - Silicon Laboratories |
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SL23EP04NZ Fiches technique(HTML) 5 Page - Silicon Laboratories |
5 / 11 page Rev 2.1, May 2, 2008 Page 5 of 11 SL23EP04NZ DC Electrical Characteristics (C-Grade and VDD=3.3V) Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C Description Symbol Condition Min Typ Max Unit Input Low Voltage VINL CLKIN and OE – – 0.8 V Input High Voltage VINH CLKIN and OE 2.0 – VDD+0.3 V Input Low Current IINL 0 < VIN < 0.8V – – 10 µA Input High Current IINH 2.4V < VIN < VDD – – 15 µA Output Low Voltage VOL IOL=12mA – – 0.4 V Output High Voltage VOH IOH=-12mA 2.4 – – V Power Supply Current IDD1 CLKIN=33MHz CL=0 (No load at outputs) – 8 12 mA Power Supply Current IDD2 CLKIN=66MHz CL=0 (No load at outputs) – 10 15 mA Power Supply Current IDD3 CLKIN=166MHz CL=0 (No load at outputs) – 14 20 mA Switching Electrical Characteristics (C-Grade and VDD=3.3V) Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C Description Symbol Condition Min Typ Max Unit Output Frequency Range FOUT1 CL=15pF 0 - 220 MHz FOUT2 CL=30pF 0 - 134 MHz Input Duty Cycle DC1 Measured at VDD/2 20 50 80 % Output Duty Cycle DC2 CL=15pF, Fout=166MHz Measured at VDD/2 45 50 55 % Output Duty Cycle DC3 CL=30pF, Fout=100MHz Measured at VDD/2 40 50 60 % Output Rise/Fall Time tr/f-1 CL=15pF, measured at 0.8V to 2.0V – – 1.2 ns Output Rise/Fall Time tr/f-2 CL=30pF, measured at 0.8V to 2.0V – – 1.6 ns Output to Output Skew SKW1 Measured at VDD/2 and Outputs are equally loaded – 60 120 ps Part to Part Skew SKW2 Measured at VDD/2 and Outputs are equally loaded – 80 160 ps Propagation Delay Time PDT Measured at VDD/2 from CLKIN to Output Clock rising edge and Outputs are equally loaded 1.5 2.5 3.5 ns Cycle-to-Cycle Jitter CCJ1 CLKIN=66MHz and CL=0 (No Load) – 35 70 ps Cycle-to-Cycle Jitter CCJ2 CLKIN=166MHz and CL=0 (No Load) – 25 50 ps Power-up Time tpu Power-up time for VDD to reach maximum specified time 0.05 – 100 ms |
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