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CDCVF2310 Fiches technique(PDF) 9 Page - Texas Instruments |
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CDCVF2310 Fiches technique(HTML) 9 Page - Texas Instruments |
9 / 23 page 25 25 25 25 25 25 25 25 25 25 Logic Control Logic Control 3 4 5 8 9 21 20 17 16 12 1Y0 1Y1 1Y2 1Y3 1Y4 2Y0 2Y1 2Y2 2Y3 2Y4 1G 2G CLK 11 13 24 CDCVF2310 www.ti.com SCAS666D – JUNE 2001 – REVISED OCTOBER 2015 8 Detailed Description 8.1 Overview The CDCVF2310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5- V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals. 8.2 Functional Block Diagram Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: CDCVF2310 |
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