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CDCLVP2106 Fiches technique(PDF) 1 Page - Texas Instruments

No de pièce CDCLVP2106
Description  12-LVPECL Output, High-Performance Clock Buffer
Download  33 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

CDCLVP2106 Fiches technique(HTML) 1 Page - Texas Instruments

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LVPECL
6
6
2
Reference
Generator
GND
GND
OUTP[11...6]
OUTN[11...6]
LVPECL
6
6
OUTP[5...0]
OUTN[5...0]
V
CC
V
AC_REF[1, 0]
V
CC
V
CC
V
CC
V
CC
V
CC
INP0
INN0
INP1
INN1
Product
Folder
Sample &
Buy
Technical
Documents
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CDCLVP2106
SCAS887B – SEPTEMBER 2009 – REVISED JANUARY 2016
CDCLVP2106 12-LVPECL Output, High-Performance Clock Buffer
1 Features
3 Description
The CDCLVP2106 is a highly versatile, low additive
1
Dual 1:6 Differential Buffer
jitter buffer that can generate 12 copies of LVPECL
Two Clock Inputs
clock outputs from two LVPECL, LVDS, or LVCMOS
Universal Inputs Can Accept LVPECL, LVDS,
inputs for a variety of communication applications. It
LVCMOS/LVTTL
has a maximum clock frequency up to 2 GHz. Each
buffer block consists of one input that feeds two
12 LVPECL Outputs
LVPECL
outputs.
The
overall
additive
jitter
Maximum Clock Frequency: 2 GHz
performance is less than 0.1 ps, RMS from 10 kHz to
Maximum Core Current Consumption: 92 mA
20 MHz, and overall output skew is as low as 20 ps,
making the device a perfect choice for use in
Very Low Additive Jitter: <100 fs, RMS in 10-kHz
demanding applications.
to 20-MHz Offset Range
2.375-V to 3.6-V Device Power Supply
The CDCLVP2106 clock buffer distributes two clock
inputs (IN0, IN1) to 12 pairs of differential LVPECL
Maximum Propagation Delay: 550 ps
clock outputs (OUT0, OUT11) with minimum skew for
Maximum Within Bank Output Skew: 20 ps
clock distribution. Each buffer block consists of one
LVPECL Reference Voltage, VAC_REF, Available
input that feeds two LVPECL clock outputs. The
for Capacitive-Coupled Inputs
inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
Industrial Temperature Range: –40°C to +85°C
The CDCLVP2106 is specifically designed for driving
Supports 105°C PCB Temperature (Measured
50-
Ω transmission lines. When driving the inputs in
single-ended
mode,
the
LVPECL
bias
voltage
with a Thermal Pad)
(VAC_REF) should be applied to the unused negative
Available in 6-mm × 6-mm, 40-Pin VQFN (RHA)
input pin. However, for high-speed performance up to
Package
2 GHz, differential mode is strongly recommended.
ESD Protection Exceeds 2000 V (HBM)
The CDCLVP2106 is characterized for operation from
–40°C to +85°C and is available in a 6-mm × 6-mm,
2 Applications
VQFN-40 package.
Wireless Communications
Device Information(1)
Telecommunications/Networking
PART NUMBER
PACKAGE
BODY SIZE (NOM)
Medical Imaging
CDCLVP2106
VQFN (40)
6.00 mm × 6.00 mm
Test and Measurement Equipment
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.


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