CDCEL824 datasheet(4/33 Pages) TI1

No de pièce	CDCEL824

Description	Programmable 2-PLL Clock Synthesizer

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Fabricant	TI1 [Texas Instruments]

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CDCEL824

SCAS945A – JUNE 2015 – REVISED SEPTEMBER 2015

www.ti.com

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

VDD

Supply voltage range

–0.5

2.5

V

VI

Input voltage range(2) (3)

–0.5

VDD + 0.5

V

VO

Output voltage range(2)

–0.5

VDD + 0.5

V

II

Input current (VI < 0, VI > VDD)

20

mA

IO

Continuous output current

50

mA

TJ

Maximum junction temperature

125

°C

Tstg

Storage temperature range

–65

150

°C

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(3)

SDA and SCL can go up to 3.6V as stated in the Recommended Operating Conditions table.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)

±2000

V(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification JESD22-C101, all

±1500

pins(2)

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN

NOM

MAX

UNIT

VDD

Device supply voltage

1.7

1.8

1.9

V

VDDOUT

Output Yx supply voltage for CDCEL824

1.7

1.9

V

VIL

Low-level input voltage LVCMOS

0.3 VDD

V

VIH

High-level input voltage LVCMOS

0.7 VDD

V

VI(thresh)

Input voltage threshold LVCMOS

0.5 VDD

V

Input voltage range S0

0

1.9

VI(S)

V

Input voltage range S1, S2, SDA, SCL; V(Ithresh) = 0.5 VDD

0

3.6

VI(CLK)

Input voltage range CLK

0

1.9

V

IOH /IOL

Output current (VDDOUT = 1.8 V)

±8

mA

CL

Output load LVCMOS

15

pF

TA

Operating free-air temperature

–40

85

°C

RECOMMENDED CRYSTAL/VCXO SPECIFICATIONS(1)

fXtal

Crystal input frequency range (fundamental mode)

10

30

MHz

ESR

Effective series resistance

100

Ω

fPR

Pulling range (0 V

≤ VCtrl ≤ 1.8 V)

(2)

±120

±150

ppm

VCtrl

Frequency control voltage

0

VDD

V

C0/C1

Pullability ratio

220

CL

On-chip load capacitance at Xin and Xout

0

20

pF

(1)

For more information about VCXO configuration, and crystal recommendation, see application report (SCAA085).

(2)

Pulling range depends on crystal-type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min ±120 ppm

applies for crystal listed in the application report (SCAA085).

4

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