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SI53320 Fiches technique(PDF) 10 Page - Silicon Laboratories

No de pièce SI53320
Description  1:5 LOW JITTER LVPECL CLOCK BUFFER
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Fabricant  SILABS [Silicon Laboratories]
Site Internet  http://www.silabs.com
Logo SILABS - Silicon Laboratories

SI53320 Fiches technique(HTML) 10 Page - Silicon Laboratories

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Si53320
10
Rev. 1.0
2.2. Input Bias Resistors
Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected.
The non-inverting input is biased with a 18.75 k
 pull-down to GND and a 75 k pull-up to VDD. The inverting input
is biased with a 75 k
 pull-up to VDD.
Figure 5. Input Bias Resistors
2.3. Glitchless Clock Input Switching
The Si53320 features glitchless switching between two valid input clocks. Figure 6 illustrates that switching
between input clocks does not generate runt pulses or glitches at the output.
Figure 6. Glitchless Input Clock Switch
The Si53320 supports glitchless switching between clocks at the same frequency. In addition, the device supports
glitchless switching between 2 input clocks that are up to 10x different in frequency. When a switchover to a new
clock is made, the output will disable low after two or three clock cycles of the previously-selected input clock. The
outputs will remain low for up to three clock cycles of the newly-selected clock, after which the outputs will start
from the newly-selected input. In the case a switchover to an absent clock is made, the output will glitchlessly stop
low and wait for edges of the newly selected clock. A switchover from an absent clock to a live clock will also be
glitchless. Note that the CLK_SEL input should not be toggled faster than 1/250th the frequency of the slower input
clock.
RPU
CLK0 or
CLK1
RPU
RPU = 75 k
RPD = 18.75 k
RPD
+
VDD
CLK1
CLK0
CLK_SEL
Qn
Note 1
Note 2
Notes:
1. Qn continues with CLK0 for 2-3 falling edges of CLK0.
2. Qn is disabled low for 2-3 falling edges of CLK1 .
3. Qn starts on the first rising edge after 1 + 2.
Note 3


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