SI53108 datasheet(9/38 Pages) SILABS

No de pièce	SI53108

Description	DB800ZL 8-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

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Si53108

Rev. 1.2

9

Table 8. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode)

Parameter

Symbol

CLK 100 MHz, 133 MHz

Unit

Notes

Min

Typ

Max

Clock Stabilization Time

TSTAB

—

1.8

ms

22

Long Term Accuracy

LACC

—

100

ppm

4,8,16

Absolute Host CLK Period (100 MHz)

TABS

9.94900

—

10.05100

ns

4,5,8

Absolute Host CLK Period (133 MHz)

TABS

7.44925

—

7.55075

ns

4,5,8

Edge _rate

1.0

—

4.0

V/ns

2,4,8

Rise/Fall Matching

TRISE_MAT/

TFALL_MAT

—

20

%

4,7,19,21

Voltage High (typ 0.7 V)

VHIGH

660

—

850

mV

3,8, 12

Voltage Low (typ 0.0 V)

VLOW

–150

—

150

mV

4,7,11

Maximum Voltage

VMAX

——

1150

mV

7

Absolute Crossing Point Voltages

VCROSS(a

bs)

300

—

550

mV

1,3,4,7,14

Total Variation of Vcross Over All

Edges

Total ∆

VCROSS

—

140

mV

4,7,15

Cycle-to-Cycle Jitter

TCCJITTER

—

50

ps

4,8,20

Duty Cycle

45

—

55

%

4,8

Maximum Voltage (Overshoot)

Vovs

——

VHigh + 0.3

V

4,7,12

Maximum Voltage (Undershoot)

Vuds

——

VLow – 0.3

V

4,7,13

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