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SI8630BD-B-IS Fiches technique(PDF) 11 Page - Silicon Laboratories |
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SI8630BD-B-IS Fiches technique(HTML) 11 Page - Silicon Laboratories |
11 / 36 page Parameter Symbol Test Condition Min Typ Max Unit All Models Output Rise Time tr CL = 15 pF See Figure 4.2 Propagation Delay Timing on page 11 — 2.5 4.0 ns Output Fall Time tf CL = 15 pF See Figure 4.2 Propagation Delay Timing on page 11 — 2.5 4.0 ns Peak Eye Diagram Jitter tJIT(PK) See Figure 2.3 Eye Diagram on page 3 — 350 — ps Common Mode Transient Immunity Si86xxxB/C/D Si86xxxT CMTI VI = VDD or 0 V VCM = 1500 V See Figure 4.3 Common- Mode Transient Immunity Test Circuit on page 11 35 60 50 100 — — kV/µs Enable to Data Valid ten1 See Figure 4.1 ENABLE Tim- ing Diagram on page 11 — 6.0 11 ns Enable to Data Tri-State ten2 See Figure 4.1 ENABLE Tim- ing Diagram on page 11 — 8.0 12 ns Input power loss to valid default output tSD See Figure 3.1 Device Behav- ior during Normal Operation on page 6 — 8.0 12 ns Start-up Time 4 tSU — 15 40 µs Note: 1. VDD1 = 5 V ±10%; VDD2 = 5 V ±10%, TA = –40 to 125 °C 2. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled-impedance PCB traces. 3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. Start-up time is the time period from the application of power to the appearance of valid data at the output. Si8630/31/35 Data Sheet Electrical Specifications silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 10 |
Numéro de pièce similaire - SI8630BD-B-IS |
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Description similaire - SI8630BD-B-IS |
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