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SI7013-A20 Fiches technique(PDF) 6 Page - Silicon Laboratories |
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SI7013-A20 Fiches technique(HTML) 6 Page - Silicon Laboratories |
6 / 45 page Si7013-A20 6 Rev. 1.1 Figure 1. I2C Interface Timing Diagram SCL Low Time tSKL 1.3 — — μs Start Hold Time tSTH 0.6 — — μs Start Setup Time tSTS 0.6 — — μs Stop Setup Time tSPS 0.6 — — μs Bus Free Time tBUF Between Stop and Start 1.3 — — μs SDA Setup Time tDS 100 — — ns SDA Hold Time tDH 100 — — ns SDA Valid Time tVD;DAT From SCL low to data valid — — 0.9 μs SDA Acknowledge Valid Time tVD;ACK From SCL low to data valid — — 0.9 μs Suppressed Pulse Width3 tSP 50 — — ns Table 3. I2C Interface Specifications1 (Continued) 1.9 VDD 3.6 V; TA = –40 to +85 °C (G grade) or –40 to +125 °C (I/Y grade) unless otherwise noted. Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. All values are referenced to VIL and/or VIH. 2. Depending on the conversion command, the Si7013 may hold the master during the conversion (clock stretch). At above 300 kHz SCL, the Si7013 may hold the master briefly for user register and device ID transactions. At the highest I2C speed of 400 kHz the stretching will be <50 μs. 3. Pulses up to and including 50 ns will be suppressed. |
Numéro de pièce similaire - SI7013-A20 |
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Description similaire - SI7013-A20 |
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