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SI5374 Fiches technique(PDF) 11 Page - Silicon Laboratories |
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SI5374 Fiches technique(HTML) 11 Page - Silicon Laboratories |
11 / 69 page Si5374 Rev. 1.1 11 Table 5. Performance Specifications VDD = 1.8 V ±5% or 2.5 V ±10%, TA = –40 to 85 °C Parameter Symbol Test Condition Min Typ Max Unit PLL Performance1 Lock Time2 Si5374B-A-xL3 tLOCKMP Start of ICAL to of LOL, FASTLOCK enabled —1 1.5 s Si5374C-A-xL — 0.8 1.0 Settle Time2 Si5374B-A-xL tSETTLE Start of ICAL to FOUT within 5 ppm of final value —1.2 1.5 s Si5374C-A-xL — 4.2 5.0 Output Clock Phase Change tP_STEP After clock switch f3 128 kHz —200 — ps Closed Loop Jitter Peaking JPK — 0.05 0.1 dB Jitter Tolerance JTOL Jitter Frequency Loop Bandwidth 5000/BW — — ns pk-pk Phase Noise fout = 622.08 MHz CKOPN 1 kHz Offset — –106 — dBc/Hz 10 kHz Offset — –114 — dBc/Hz 100 kHz Offset — –116 — dBc/Hz 1 MHz Offset — –132 — dBc/Hz Spurious Noise SPSPUR Max spur @ n x F3 (n 1, n x F3 < 100 MHz) —–70 — dBc Jitter Generation JGEN fIN =fOUT =622.08MHz, BW = 120 Hz LVPECL output 12 kHz–20 MHz — 350 410 fs rms 50 kHz–80 MHz — 410 — fs rms Notes: 1. fin = fout = 622.08 MHz; BW = 7 Hz; LVDS, OSC = .121.109 MHz. 2. Lock and settle time performance is dependent on the frequency plan and the OSC_P/OSC_N reference frequency and LOCKT setting (see application note, "AN803: Lock and Settling Time Considerations for the Si5324/27/69/74 Any-Frequency Jitter Attenuating Clock ICs". Visit the Silicon Labs Technical Support web page at: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support request regarding the lock time of your frequency plan. 3. LOCKT = 3.3 ms. |
Numéro de pièce similaire - SI5374 |
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Description similaire - SI5374 |
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