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SI5346 Fiches technique(PDF) 1 Page - Silicon Laboratories

No de pièce SI5346
Description  DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS
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Fabricant  SILABS [Silicon Laboratories]
Site Internet  http://www.silabs.com
Logo SILABS - Silicon Laboratories

SI5346 Fiches technique(HTML) 1 Page - Silicon Laboratories

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Rev. 1.1 9/15
Copyright © 2015 by Silicon Laboratories
Si5347/46
Si5347/46
D UAL/Q UAD DSPLL A NY-F REQUENCY, A NY-O UTPUT J ITTER A TTENUATORS
Features
Device Selector Guide
Applications
Description
The Si5347 is a high performance jitter attenuating clock multiplier which integrates four
any-frequency DSPLLs for applications that require maximum integration and independent
timing paths. The Si5346 is a dual DSPLL version in a smaller package. Each DSPLL has
access to any of the four inputs and can provide low jitter clocks on any of the device
outputs. Based on 4th generation DSPLL technology, these devices provide any-frequency
conversion with typical jitter performance under 100 fs. Each DSPLL supports independent
free-run, holdover modes of operation, as well as automatic and hitless input clock
switching. The Si5347/46 is programmable via a serial interface with in-circuit
programmable non-volatile memory so that it always powers up in a known configuration.
Programming the Si5347/46 is easy with Silicon Labs’ ClockBuilder Pro software. Factory
pre-programmed devices are also available.
 Four or two independent DSPLLs in a
single monolithic IC
 Each DSPLL generates any output
frequency from any input frequency
 Input frequency range:

Differential: 8 kHz to 750 MHz

LVCMOS: 8 kHz to 250 MHz
 Output frequency range:

Differential: up to 712.5 MHz

LVCMOS: up to 250 MHz
 Ultra low jitter:
<100 fs typ (12 kHz–20 MHz)
 Flexible crosspoints route any input to
any output clock
 Programmable jitter attenuation
bandwidth per DSPLL: 0.1 Hz to 4 kHz
programming range
 Highly configurable outputs compatible
with LVDS, LVPECL, LVCMOS, CML,
and HCSL with programmable signal
amplitude
 Status monitoring (LOS, OOF, LOL)
 Hitless input clock switching: automatic
or manual
 Locks to gapped clock inputs
 Automatic free-run and holdover modes
 Fastlock feature for low nominal
bandwidths
 Glitchless on-the-fly DSPLL frequency
changes
 DCO mode: as low as 0.01 ppb steps
per DSPLL
 Core voltage:

VDD: 1.8 V ±5%

VDDA: 3.3 V ±5%
 Independent output clock supply pins:
3.3, 2.5, or 1.8 V
 Output-output skew:

<20 ps (typ) per DSPLL
 Serial interface: I2C or SPI
 In-circuit programmable with non-volatile
OTP memory
 ClockBuilderTM Pro software tool
simplifies device configuration
 Si5347: Quad DSPLL, 4 input,
4 or 8 output, 64 QFN
 Si5346: Dual DSPLL, 4 input,
4 output, 44 QFN
 Temperature range: –40 to +85 °C
 Pb-free, RoHS-6 compliant
Grade
PLLs/OUTs
Max Output Freq
Frequency Synthesis Modes
Si5347A
4/8
712.5 MHz
Integer + Fractional
Si5347C
4/4
712.5 MHz
Integer + Fractional
Si5346A
2/4
712.5 MHz
Integer + Fractional
Si5347B
4/8
350 MHz
Integer + Fractional
Si5347D
4/4
350 MHz
Integer + Fractional
Si5346B
2/4
350 MHz
Integer + Fractional
 OTN Muxponders and Transponders
 10/40/100G network line cards
 GbE/10 GbE/100 GbE Synchronous
Ethernet (ITU-T G.8262)
 Carrier Ethernet switches
 Broadcast video
Functional Block Diagram
Ordering Information:
See section 8
9x9 mm
7x7 mm
Si5347
DSPLL
A
DSPLL
B
DSPLL
D
DSPLL
C
IN1
IN2
IN3
IN0
OUT7
OUT6
OUT5
OUT1
OUT4
OUT3
OUT2
OUT0
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷FRAC
÷FRAC
÷FRAC
÷FRAC
NVM
I
2C/SPI
Control/
Status
XTAL/
REFCLK
XB
XA
OSC
S i534 6
DSPL L
A
DSPL L
B
IN 1
IN 2
IN 3
IN 0
OUT 1
OUT 3
OUT 2
OUT 0
÷IN T
÷IN T
÷IN T
÷IN T
÷ F RAC
÷ F RAC
÷ F RAC
÷ F RAC
NV M
I
2 C/S PI
C ontro l/
Sta tus
XTAL /
RE F C L K
XB
XA
OS C


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