SI5341 datasheet(7/56 Pages) SILABS

No de pièce	SI5341

Description	LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

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Fabricant	SILABS [Silicon Laboratories]

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Si5341/40

Rev. 1.0

7

Table 3. Input Specifications

(VDD =1.8 V ±5%, VDDA =3.3 V ±5%, TA = –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Differential or Single-Ended/LVCMOS — AC-Coupled (IN0/IN0, IN1/IN1, IN2/IN2, FB_IN/FB_IN)

Input Frequency Range

fIN

Differential

10

—

750

MHz

Single-ended/LVCMOS

10

—

250

Input Voltage Swing5

VIN

Differential AC Coupled

fin < 250 MHz

100

—

1800

mVpp_se

Differential AC Coupled

250 MHz < fin < 750 MHz

225

—

1800

mVpp_se

Single-ended AC Coupled

fin < 250 MHz

100

—

3600

mVpp_se

Slew Rate1, 2

SR

400

—

V/µs

Duty Cycle

DC

40

—

60

%

Capacitance

CIN

—2

—

pF

DC-Coupled CMOS Input Buffer (IN0, IN1, IN2)4

Input Frequency

fIN

10

—

250

MHz

Input Voltage

VIL

–0.2

—

0.33

V

VIH

0.49

—

V

Slew Rate1, 2

SR

400

—

V/µs

Duty Cycle

DC

Clock Input

40

—

60

%

Minimum Pulse Width

PW

Pulse Input

1.6

—

ns

Input Resistance

RIN

—8

—

kΩ

Differential or Single-Ended/LVCMOS Clock at XA/XB

Input Frequency Range

fIN

Frequency range for best

output

jitter performance

48

—

200

MHz

10

—

200

MHz

Input Single-ended Voltage Swing

VIN_SE

365

—

2000

mVpp_se

Notes:

1. Imposed for jitter performance.

2. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 - 0.2) * VIN_Vpp_se) / SR.

3. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD.

4. DC-coupled CMOS Input Buffer selection is not supported in ClockBuilder Pro for new designs. For single-ended

LVCMOS inputs to IN0,1,2 it is required to ac-couple into the differential input buffer.

5. Voltage swing is specified as single-ended mVpp.

6. Contact Silicon Labs Technical Support for more details.

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