Moteur de recherche de fiches techniques de composants électroniques |
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SI599 Fiches technique(PDF) 7 Page - Silicon Laboratories |
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SI599 Fiches technique(HTML) 7 Page - Silicon Laboratories |
7 / 28 page Si598/Si599 Rev. 1.0 7 Table 4. CLK± Output Levels and Symmetry (Typical values TA = 25 ºC, VDD = 3.3 V, min/max limits VDD = 1.8 ±5%, 2.5 or 3.3 V ±10%, TA = –40 to 85 ºC unless otherwise noted) Parameter Symbol Test Condition Min Typ Max Units LVPECL Output Option1 VO mid-level VDD – 1.42 — VDD – 1.25 V VOD swing (diff) 1.1 — 1.9 VPP VSE swing (single-ended) 0.55 — 0.95 VPP LVDS Output Option2 VO mid-level 1.125 1.20 1.275 V VOD swing (diff) 0.5 0.7 0.9 VPP CML Output Option2 VO 2.5/3.3 V option mid-level — VDD – 1.30 — V 1.8 V option mid-level — VDD – 0.36 — V VOD 2.5/3.3 V option swing (diff) 1.10 1.50 1.90 VPP 1.8 V option swing (diff) 0.35 0.425 0.50 VPP CMOS Output Option3 VOH IOH =32mA 0.8 x VDD — VDD V VOL IOL =32mA — — 0.4 V Rise/Fall Time (20/80 %) tR, tF LVPECL/LVDS/CML — — 350 ps CMOS with CL =15pF — 1 — ns Symmetry (duty cycle) SYM LVPECL: VDD – 1.3 V (diff) LVDS: 1.25 V (diff) CMOS: VDD/2 48 — 52 % Notes: 1. 50 to VDD – 2.0 V. 2. Rterm =100 (differential). 3. CL = 15 pF sinking or sourcing 12 mA for VDD = 3.3 V, 6 mA for VDD = 2.5 V, 3 mA for VDD =1.8 V. |
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