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SI554 Fiches technique(PDF) 6 Page - Silicon Laboratories |
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SI554 Fiches technique(HTML) 6 Page - Silicon Laboratories |
6 / 15 page Si554 6 Rev. 1.1 Phase Jitter (RMS)1,2,5 for FOUT 10 to 160 MHz CMOS Output Only J Kv = 33 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 20 MHz — — 0.63 0.62 — — ps Kv = 45 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 20 MHz — — 0.63 0.62 — — ps Kv = 90 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 20 MHz — — 0.67 0.66 — — ps Kv = 135 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 20 MHz — — 0.74 0.72 — — ps Kv = 180 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 20 MHz — — 0.83 0.8 — — ps Kv = 356 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 20 MHz — — 1.26 1.2 — — ps Table 6. CLK± Output Period Jitter Parameter Symbol Test Condition Min Typ Max Units Period Jitter* JPER RMS — 2 — ps Peak-to-Peak — 14 — ps *Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information. Table 5. CLK± Output Phase Jitter (Continued) Parameter Symbol Test Condition Min Typ Max Units Notes: 1. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information. 3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply rejection (PSR) advantage of Si55x versus SAW-based solutions. 4. Max jitter for LVPECL output with VC=1.65V, VDD=3.3V, 155.52 MHz. 5. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz, 2 MHz for 10 MHz < FOUT <50 MHz. |
Numéro de pièce similaire - SI554 |
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Description similaire - SI554 |
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