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54ACTQ373D Fiches technique(PDF) 2 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No de pièce 54ACTQ373D
Description  Quiet Series Octal Transparent Latch with TRI-STATE Outputs
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Fabricant  NSC [National Semiconductor (TI)]
Site Internet  http://www.national.com
Logo NSC - National Semiconductor (TI)

54ACTQ373D Fiches technique(HTML) 2 Page - National Semiconductor (TI)

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Connection Diagrams
Functional Description
The ’ACQ/’ACTQ373 contains eight D-type latches with
TRI-STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on the D
n inputs enters the latches. In
this condition the latches are transparent, i.e., a latch output
will change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
sition of LE. The TRI-STATE standard outputs are controlled
by the Output Enable (OE) input. When OE is LOW, the stan-
dard outputs are in the 2-state mode. When OE is HIGH, the
standard outputs are in the high impedance mode but this
does not interfere with entering new data into the latches.
Truth Table
Inputs
Outputs
LE
OE
D
n
O
n
XHX
Z
HL
L
L
HLH
H
LL
X
O
0
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH to Low transition of Latch Enable
Logic Diagram
Pin Assignment for
DIP and Flatpak
DS100238-3
Pin Assignment
for LCC
DS100238-4
DS100238-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2


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