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TMP275AQDRQ1 Fiches technique(PDF) 9 Page - Texas Instruments |
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TMP275AQDRQ1 Fiches technique(HTML) 9 Page - Texas Instruments |
9 / 31 page 9 TMP275-Q1 www.ti.com SBOS760A – NOVEMBER 2015 – REVISED JANUARY 2016 Product Folder Links: TMP275-Q1 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Digital Temperature Output The temperature register of the TMP275-Q1 is a 12-bit, read-only register that stores the output of the most recent conversion. Two bytes must be read to obtain data, and are described in Table 5 and Table 6. Note that byte 1 is the most significant byte and is followed by byte 2, the least significant byte. The first 12 bits are used to indicate temperature, with all remaining bits equal to zero. The least significant byte does not have to be read if that information is not needed. The data format for temperature is summarized in Table 1. Following power-up or reset, the Temperature register reads 0°C until the first conversion is complete. The user can obtain 9, 10, 11, or 12 bits of resolution by addressing the Configuration register and setting the resolution bits accordingly. For 9-, 10-, or 11-bit resolution, the most significant bits (MSBs) in the Temperature register are used with the unused least significant bits (LSBs) set to zero. Table 1. Temperature Data Format TEMPERATURE (°C) DIGITAL OUTPUT BINARY HEX 128 0111 1111 1111 7FF 127.9375 0111 1111 1111 7FF 100 0110 0100 0000 640 80 0101 0000 0000 500 75 0100 1011 0000 4B0 50 0011 0010 0000 320 25 0001 1001 0000 190 0.25 0000 0000 0100 004 0 0000 0000 0000 000 –0.25 1111 1111 1100 FFC –25 1110 0111 0000 E70 –55 1100 1001 0000 C90 7.3.2 Serial Interface The TMP275-Q1 operates only as a slave device on the SMBus, two-wire, and I2C interface-compatible bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The SDA and SCL pins feature integrated spike-suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP275-Q1 supports the transmission protocol for fast (up to 400 kHz) and high-speed (up to 2.38 MHz) modes. All data bytes are transmitted most significant bit (MSB) first. 7.3.3 Bus Overview The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. To address a specific device a START condition is initiated, indicated by pulling the data line (SDA) from a high to a low logic level when SCL is high. All slaves on the bus shift in the slave address byte, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an Acknowledge bit and pulling SDA low. Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge bit. During data transfer, SDA must remain stable when SCL is high because any change in SDA when SCL is high is interpreted as a control signal. When all data are transferred, the master generates a STOP condition indicated by pulling SDA from low to high when SCL is high. |
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