FAN48632UC33X datasheet(11/13 Pages) FAIRCHILD

No de pièce	FAN48632UC33X

Description	2.5 MHz, 2.0 A Pulsed-Load Synchronous TinyBoost

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Fabricant	FAIRCHILD [Fairchild Semiconductor]

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FAN48632

• Rev. 1.0.3

11

Application Information

Output Capacitance (COUT)

Stability

The effective capacitance (CEFF) of small, high-value, ceramic

capacitors decreases as bias voltage increases.

FAN48632 is guaranteed for stable operation with the

minimum value of CEFF (CEFF(MIN)) of 14 F.

CEFF varies with manufacturer, material, and case size.

Inductor Selection

The recommended nominal inductance value is 0.47

H.

FAN48632 employs valley-current limiting; peak inductor

current can exceed4.4 A for a short duration during overload

conditions. Saturation effects cause the inductor current ripple

to become higher under high loading as only valley of the

inductor current ripple is controlled..

Startup

Input current limiting is in effect during soft-start, which limits

the current available to charge COUT and any additional

capacitance on the VOUT line. If the output fails to achieve

regulation within the limits described in the Startup section, a

FAULT occurs, causing the circuit to shut down then restart

after a significant time period. If the total combined output

capacitance is very high, the circuit may not start on the first

attempt, but eventually achieves regulation if no load is

present. If a high-current load and high capacitance are both

present during soft-start, the circuit may fail to achieve

regulation and continually attempts soft-start, only to have

the output capacitance discharged by the load when in a

FAULT state.

Output Voltage Ripple

Output voltage ripple is inversely proportional to COUT. During

tON, when the boost switch is on, all load current is supplied by

COUT. Output ripple is calculated as:

OUT

)

(

C

I

t

V

LOAD

ON

P

RIPPLE







and

EQ. 3























OUT

IN

SW

ON

V

t

D

t

1

therefore:

EQ. 4

OUT

)

(

1

C

I

V

t

V

LOAD

OUT

IN

SW

P

RIPPLE























and

EQ. 5

SW

f

t

1



EQ. 6

As can be seen from EQ. 5, the maximum VRIPPLE occurs

when VIN is at minimum and ILOAD is at maximum.

2.0 A Pulsed Loads for GSM Applications

The FAN48632 can support 2 A load pulses for GSM and

GSM Edge applications, according to the minimum VIN levels

shown in Figure 23.

Figure 23. Minimum VIN for 2 A GSM Pulse, 3.5 VOUT

Results shown use circuit/components of Figure 1

with device

mounted on standard evaluation platform (layout Figure 24).

Layout Recommendation

To minimize spikes at VOUT, COUT must be placed as close as

possible to PGND and VOUT, as shown in Figure 24. The

associated PGND and VOUT routes are best made directly on

the top copper layer, rather than thru vias.

For thermal reasons, it is suggested to maximize the pour

area for all planes other than SW. Especially the ground pour

should be set to fill all available PCB surface area and tied to

internal layers with a cluster of thermal vias.

Figure 24. Layout Recommendation

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