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54ABT373 Fiches technique(PDF) 1 Page - National Semiconductor (TI) |
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54ABT373 Fiches technique(HTML) 1 Page - National Semiconductor (TI) |
1 / 14 page 54ABT373 Octal Transparent Latch with TRI-STATE® Outputs General Description The ’ABT373 consists of eight latches with TRI-STATE out- puts for bus organized system applications. The flip-flops ap- pear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. Features n TRI-STATE outputs for bus interfacing n Output sink capability of 48 mA, source capability of 24 mA n Guaranteed multiple output switching specifications n Output switching specified for both 50 pF and 250 pF loads n Guaranteed simultaneous switching, noise level and dynamic threshold performance n Guaranteed latchup protection n High impedance glitch free bus loading during entire power up and power down n Nondestructive hot insertion capability n Standard Microcircuit Drawing (SMD) 5962-9321801 Ordering Code Military Package Number Package Description 54ABT373J-QML J20A 20-Lead Ceramic Dual-In-Line 54ABT373W-QML W20A 20-Lead Cerpack 54ABT373E-QML E20A 20-Lead Ceramic Leadless Chip Carrier, Type C Connection Diagrams Pin Names Description D 0–D7 Data Inputs LE Latch Enable Input (Active HIGH) OE Output Enable Input (Active LOW) O 0–O7 TRI-STATE Latch Outputs TRI-STATE® is a registered trademark of National Semiconductor Corporation. Pin Assignment for DIP and Flatpak DS100206-1 Pin Assignment for LCC DS100206-2 July 1998 © 1998 National Semiconductor Corporation DS100206 www.national.com |
Numéro de pièce similaire - 54ABT373 |
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Description similaire - 54ABT373 |
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