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TMP107BID Fiches technique(PDF) 6 Page - Texas Instruments |
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TMP107BID Fiches technique(HTML) 6 Page - Texas Instruments |
6 / 40 page VIH VIL tRISE tJITTER tJITTER tSKEW tSKEW tBAUD tBAUD tFALL From Host to TMP107 From TMP107 to Host or From TMP107 to Next TMP107 in Daisy-Chain tJITTER tJITTER tRISE tFALL VIH VIL TMP107 SBOS716B – MAY 2015 – REVISED SEPTEMBER 2015 www.ti.com 6.6 Timing Requirements MIN NOM MAX UNIT FROM HOST TO THE TMP107 1/tBAUD SMAART bus baud rate 4.8 115.4 kBd tRISE + tJITTER SMAART bus transition from low to high + edge timing variance 15 % of (1/baud) tFALL + tJITTER SMAART bus transition from high to low + edge timing variance 15 % of (1/baud) FROM THE TMP107 TO HOST OR NEXT TMP107 IN DAISY-CHAIN tJITTER Edge timing variance 1 µs tSKEW Average phase shift between IO1 and IO2 33 ns tRISE SMAART bus transition from low to high, 10-pF load 10 ns tFALL SMAART bus transition from high to low, 10-pF load 10 ns Figure 1. Timing Diagram 6 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TMP107 |
Numéro de pièce similaire - TMP107BID |
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