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TMP75CID Fiches technique(PDF) 10 Page - Texas Instruments |
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TMP75CID Fiches technique(HTML) 10 Page - Texas Instruments |
10 / 31 page TMP75C SBOS707B – APRIL 2014 – REVISED AUGUST 2014 www.ti.com 7.3.3 Serial Interface The TMP75C operates as a slave device only on the two-wire bus and SMBus. Connections to the bus are made using the open-drain I/O lines, SDA and SCL. The SDA and SCL pins feature integrated spike-suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP75C supports the transmission protocol for both fast (1 kHz to 400 kHz) and high-speed (1 kHz to 3 MHz) modes. All data bytes are transmitted MSB first. 7.3.3.1 Bus Overview The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the start and stop conditions. To address a specific device, initiate a start condition by pulling the data line (SDA) from a high to a low logic level while SCL is high. All slaves on the bus shift in the slave address byte; the last bit indicates whether a read or write operation follows. During the ninth clock pulse, the slave being addressed responds to the master by generating an acknowledge bit and pulling SDA low. Data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During data transfer, SDA must remain stable while SCL is high because any change in SDA while SCL is high is interpreted as a start or stop signal. After all data have been transferred, the master generates a stop condition indicated by pulling SDA from low to high, while SCL is high. 7.3.3.2 Serial Bus Address To communicate with the TMP75C, the master must first communicate with slave devices using a slave address byte. The slave address byte consists of seven address bits, and a direction bit indicating the intent of executing either a read or write operation. The TMP75C features three address pins that allow up to eight devices to be addressed on a single bus. The TMP75C latches the status of the address pins at the start of a communication. Table 2 describes the pin logic levels and the corresponding address values. Table 2. Address Pin Connections and Slave Addresses DEVICE TWO-WIRE ADDRESS A2 A1 A0 1001000 GND GND GND 1001001 GND GND VS 1001010 GND VS GND 1001011 GND VS VS 1001100 VS GND GND 1001101 VS GND VS 1001110 VS VS GND 1001111 VS VS VS 7.3.3.3 Writing and Reading Operation Accessing a particular register on the TMP75C is accomplished by writing the appropriate value to the pointer register. The value for the pointer register is the first byte transferred after the slave address byte with the R/W bit low. Every write operation to the TMP75C requires a value for the pointer register (see Figure 9). When reading from the TMP75C, the last value stored in the pointer register by a write operation is used to determine which register is read by a read operation. To change the register pointer for a read operation, a new value must be written to the pointer register. This action is accomplished by issuing a slave address byte with the R/W bit low, followed by the pointer register byte. No additional data are required. The master can then generate a start condition and send the slave address byte with the R/W bit high to initiate the read command. See Figure 10 for details of this sequence. If repeated reads from the same register are desired, there is no need to continually send the pointer register bytes because the TMP75C stores the pointer register value until it is changed by the next write operation. Note that register bytes are sent with the most significant byte first, followed by the least significant byte. 10 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: TMP75C |
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