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LC717A10PJ-AH Fiches technique(PDF) 2 Page - ON Semiconductor |
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LC717A10PJ-AH Fiches technique(HTML) 2 Page - ON Semiconductor |
2 / 14 page LC717A10PJ No.A2214-2/14 Specifications Absolute Maximum Ratings at Ta = +25 C Parameter Symbol Ratings (VSS = 0V) Unit Remarks Supply voltage VDD -0.3 to +6.5 V Input voltage VIN -0.3 to VDD+0.3 V *1 Output voltage VOUT -0.3 to VDD+0.3 V *2 Power dissipation Pd max 160 mW Ta = +105 C, Mounted on a substrate *3 Peak output current IOP ±8 mA Per a pin Duty ratio 50% *2 Total output current IOA ±40 mA LSI outputs total value Duty ratio 25% *2 *1) Apply to Cin0 to 15, Cref, CrefAdd, nRST, SCL, SDA, SA0, SA1, SCK, SI, nCS *2) Apply to Cdrv, SDA, SO, INTOUT *3) Single-layer glass epoxy board (76.1 114.31.6t mm) Recommended Operating Conditions Parameter Symbol Conditions min typ max Unit Remarks Operating supply voltage VDD 2.6 5.5 V Supply ripple + noise Vpp ±20 mV *1 Operating temperature Topr -40 25 105 C *1) We recommend connecting large and small capacitance between VDD and VSS. In this case, the small capacitance is equal to or more than 0.1 F, and layout nearby LSI. Electrical Characteristics at VSS = 0V, VDD = 2.6 to 5.5V, Ta -40 to +105C * Unless otherwise specified, the Cdrv drive frequency is fCDRV = 143kHz. * Not tested at low temperature before shipment. Parameter Symbol Conditions min typ max Unit Remarks Capacitance detection resolution N 8 bit Output noise RMS NRMS minimum gain setting ±1.0 LSB *1 *3 Input offset capacitance adjustment range CoffRANGE ±8.0 pF *1 *3 Input offset capacitance adjustment resolution CoffRESO 8 bit Cin offset drift CinDRIFT minimum gain setting ±8 LSB *1 Cin detection sensitivity CinSENSE minimum gain setting 0.052 0.108 LSB/fF *2 Cin pin leak current ICin Cin = Hi-Z ±25 ±500 nA Cin allowable parasitic input capacitance CinSUB Cin against VSS 30 pF *1 *3 Cdrv drive frequency fCDRV 100 143 186 kHz VDD = 5V ±3%, 54.8kHz setting 50.4 59.45 68.5 kHz *1 nRST minimum pulse width tNRST 1 s Power-on reset time tPOR 20 ms Power-on reset operation condition: Hold time tPOROP 10 ms *1 Power-on reset operation condition: Input voltage VPOROP 0.1 V *1 Power-on reset operation condition: Power supply rise rate tVDD 0V to VDD 1 V/ms *1 Long interval time TIVAL 40 101 162 ms Continued to the next page. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. |
Numéro de pièce similaire - LC717A10PJ-AH |
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Description similaire - LC717A10PJ-AH |
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