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SN74LS163AMEL Fiches technique(PDF) 3 Page - ON Semiconductor

No de pièce SN74LS163AMEL
Description  BCD Decade Counters 4?묪it Binary Counters
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Fabricant  ONSEMI [ON Semiconductor]
Site Internet  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

SN74LS163AMEL Fiches technique(HTML) 3 Page - ON Semiconductor

  SN74LS163AMEL Datasheet HTML 1Page - ON Semiconductor SN74LS163AMEL Datasheet HTML 2Page - ON Semiconductor SN74LS163AMEL Datasheet HTML 3Page - ON Semiconductor SN74LS163AMEL Datasheet HTML 4Page - ON Semiconductor SN74LS163AMEL Datasheet HTML 5Page - ON Semiconductor SN74LS163AMEL Datasheet HTML 6Page - ON Semiconductor SN74LS163AMEL Datasheet HTML 7Page - ON Semiconductor SN74LS163AMEL Datasheet HTML 8Page - ON Semiconductor  
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SN74LS161A, SN74LS163A
http://onsemi.com
3
LS161A • LS163A
0123
4
5
6
7
8
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10
11
12
13
14
15
Count Enable = CEP • CET • PE
TC for LS161A & LS163A = CET • Q0 • Q1 • Q2 • Q3
Preset = PE • CP + (rising clock edge)
Reset = MR (LS161A)
Reset = SR • CP + (rising clock edge)
Reset = (LS163A)
STATE DIAGRAM
LOGIC EQUATIONS
FUNCTIONAL DESCRIPTION
The LS161A/163A are 4-bit synchronous counters with
a synchronous Parallel Enable (Load) feature. The counters
consist of four edge-triggered D flip-flops with the
appropriate data routing networks feeding the D inputs. All
changes of the Q outputs (except due to the asynchronous
Master Reset in the LS161A) occur as a result of, and
synchronous with, the LOW to HIGH transition of the Clock
input (CP). As long as the set-up time requirements are met,
there are no special timing or activity constraints on any of
the mode control or data inputs.
Three control inputs — Parallel Enable (PE), Count
Enable Parallel (CEP) and Count Enable Trickle (CET) —
select the mode of operation as shown in the tables below.
The Count Mode is enabled when the CEP, CET, and PE
inputs are HIGH. When the PE is LOW, the counters will
synchronously load the data from the parallel inputs into the
flip-flops on the LOW to HIGH transition of the clock.
Either the CEP or CET can be used to inhibit the count
sequence. With the PE held HIGH, a LOW on either the CEP
or CET inputs at least one set-up time prior to the LOW to
HIGH clock transition will cause the existing output states
to be retained. The AND feature of the two Count Enable
inputs (CET•CEP) allows synchronous cascading without
external gating and without delay accumulation over any
practical number of bits or digits.
The Terminal Count (TC) output is HIGH when the Count
Enable Trickle (CET) input is HIGH while the counter is in
its maximum count state (HLLH for the BCD counters,
HHHH for the Binary counters). Note that TC is fully
decoded and will, therefore, be HIGH only for one count
state.
The LS161A and LS163A count modulo 16 following a
binary sequence. They generate a TC when the CET input is
HIGH while the counter is in state 15 (HHHH). From this
state they increment to state 0 (LLLL).
The Master Reset (MR) of the LS161A is asynchronous.
When the MR is LOW, it overrides all other input conditions
and sets the outputs LOW. The MR pin should never be left
open. If not used, the MR pin should be tied through a
resistor to VCC, or to a gate output which is permanently set
to a HIGH logic level.
The active LOW Synchronous Reset (SR) input of the
LS163A acts as an edge-triggered control input, overriding
CET, CEP and PE, and resetting the four counter flip-flops
on the LOW to HIGH transition of the clock. This simplifies
the design from race-free logic controlled reset circuits, e.g.,
to reset the counter synchronously after reaching a
predetermined value.
MODE SELECT TABLE
*SR
PE
CET
CEP
Action on the Rising Clock Edge (
)
L
X
X
X
RESET (Clear)
H
L
X
X
LOAD (Pn → Qn)
H
H
H
H
COUNT (Increment)
H
H
L
X
NO CHANGE (Hold)
H
H
X
L
NO CHANGE (Hold)
*For the LS163A only.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care


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