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ML2036CS Fiches technique(PDF) 8 Page - Micro Linear Corporation |
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ML2036CS Fiches technique(HTML) 8 Page - Micro Linear Corporation |
8 / 12 page ML2036 8 FUNCTIONAL DESCRIPTION (Continued) The crystal must have the following characteristics: 1. Parallel resonant type 2. Frequency: 3MHz to 12.4MHz 3. Maximum equivalent series resistance of 15 W at a drive levels of 1µW to 200µW, and 30 W at drive levels of 10nW to 1µW 4. Typical load capacitance: 18pF 5. Maximum case capacitance: 7pF The frequency of oscillation will be a function of the crystal parameters and PC board capacitance. Crystals that meet these requirements at 12.352000MHz are M-tron 3709-010 12.352 for 0ºC to 70ºC and 3709-020 12.352 for -40ºC to 85ºC operation. The ML2036 has two clock outputs that can be used to drive other external devices. The CLK OUT 1 output is a buffered output from the oscillator divided by 2. The CLK OUT 2 output is a buffered output from the oscillator divided by 8. SERIAL DIGITAL INTERFACE The digital interface consists of a shift register and data latch. The serial 16-bit data word on SID is clocked into a 16-bit shift register on rising edges of the serial shift clock, SCK. The LSB should be shifted in first and the MSB last as shown in Figure 4. The data that has been shifted into the shift register is loaded into a 16-bit data latch on the falling edge of LATI. To insure that true data is loaded into the data latch from the shift register, LATI falling edge should occur when SCK is low, as shown in figure 1. LATI should be low while shifting data into the shift register to avoid inadvertently entering the power down mode. Note that all data is entered and latched on the edges, not levels, of SCK and LATI. INHIBIT AND POWER DOWN MODES The ML2036 has an inhibit mode and a power down mode which are controlled by the three-level PDN–INH input as described in Table 1. If a logic "1", (VI3) is applied to the PDN–INH pin, the power down mode is entered by entering all zeros in the shift register and applying a logic "1" to LATI and holding it high. A zero data detect circuit detects when all bits in the shift register are zeros. In this state, the power consumption is reduced to 11.5mW max, and VOUT goes to 0V as shown in Figure 6 and appears as 10k W to AGND. CLK IN can be left active or removed during power down mode. Also, the ML2036 can be placed in the power down mode by applying a logic “0” to the PDN–INH pin, regardless of the contents of the shift register and the state of LATI. If VSS to VSS + 0.5V (VI2) is applied to the PDN–INH pin, the inhibit mode is entered by shifting all zeros into the shift register and applying a logic “1” to the LATI pin. Once the inhibit mode is entered VOUT will complete the last half cycle of the sinewave and then be held at approximately VOS, such that no voltage step occurs, as shown in Figure 6. POWER SUPPLIES The analog circuits in ML2036 are powered from VCC to VSS and are referenced to AGND. The digital circuits in the device are powered from VCC to DGND. It is recommended that AGND and DGND be connected together close to the device, and have a good connection back to the power source. It is recommended that the power supplies to the device should be bypassed by placing decoupling capacitors from VCC to AGND and VSS to AGND as physically close to the device as possible. |
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Description similaire - ML2036CS |
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