LM20136

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SNVS564B – JANUARY 2009 – REVISED APRIL 2013

OPERATION DESCRIPTION

General

The LM20136 switching regulator features all of the functions necessary to implement an efficient low voltage

buck regulator using a minimum number of external components. This easy to use regulator features two

integrated switches and is capable of supplying up to 6A of continuous output current. The regulator utilizes peak

current mode control with nonlinear slope compensation to optimize stability and transient response over the

entire output voltage range. Peak current mode control also provides inherent line feed-forward, cycle-by-cycle

current limiting and easy loop compensation. The internal oscillator can synchronize up to 1.5 MHz minimizing

the inductor size while still achieving efficiencies up to 96%. The precision internal voltage reference allows the

output to be set as low as 0.8V. Fault protection features include: current limiting, thermal shutdown, over voltage

protection, and shutdown capability. The device is available in the HTSSOP package featuring an exposed pad

to aid thermal dissipation. The LM20136 can be used in numerous applications to efficiently step-down from a 5V

or 3.3V bus. The typical application circuit for the LM20136 is shown in Figure 30 in the design guide.

Precision Enable

The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal.

This pin is a precision analog input that enables the device when the voltage exceeds 1.18V (typical). The EN pin

has 66 mV of hysteresis and will disable the output when the enable voltage falls below 1.11V (typical). If the EN

voltage. The precision enable circuitry will remain active even when the device is disabled.

Frequency Synchronization

The frequency synchronization pin (SYNC) allows the switching frequency of the device to be controlled with an

external clock signal. This feature allows the user to synchronize multiple converters, avoiding undesirable

frequency bands of operation. Multiple devices can be configured to switch out of phase reducing input capacitor

requirements and EMI of the power supply system.

The turn on of the high-side switch will lock-on to the rising edge of the SYNC pin input. The logic low level for

the input clock must be below 0.8V and the logic high level must exceed 2.0V to ensure proper operation. The

device will synchronize to frequencies from 500 kHz to 1.5 MHz. If the synchronization clock is removed or not

present during startup, the oscillator of the device will run at approximately 410 kHz. If the SYNC pin is not used

it should be connected to ground.

Peak Current Mode Control

In most cases, the peak current mode control architecture used in the LM20136 only requires two external

components to achieve a stable design. The compensation can be selected to accommodate any capacitor type

or value. The external compensation also allows the user to set the crossover frequency and optimize the

transient performance of the device.

For duty cycles above 50% all current mode control buck converters require the addition of an artificial ramp to

avoid sub-harmonic oscillation. This artificial linear ramp is commonly referred to as slope compensation. What

makes the LM20136 unique is the amount of slope compensation will change depending on the output voltage.

When operating at high output voltages the device will have more slope compensation than when operating at

lower output voltages. This is accomplished in the LM20136 by using a non-linear parabolic ramp for the slope

compensation. The parabolic slope compensation of the LM20136 is much better than the traditional linear slope

compensation because it optimizes the stability of the device over the entire output voltage range.

Current Limit

The precise current limit of the LM20136 is set at the factory to be within 10% over the entire operating

temperature range. This enables the device to operate with smaller inductors that have lower saturation currents.

When the peak inductor current reaches the current limit threshold, an over current event is triggered and the

internal high-side FET turns off and the low-side FET turns on allowing the inductor current to ramp down until

the next switching cycle. For each sequential over-current event, the reference voltage is decremented and PWM

pulses are skipped resulting in a current limit that does not aggressively fold back for brief over-current events,

while at the same time providing frequency and voltage foldback protection during hard short circuit conditions.

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