TC7116ACLW datasheet(10/22 Pages) MICROCHIP

No de pièce	TC7116ACLW

Description	3-1/2 Digit Analog-to-Digital Converters with Hold

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Fabricant	MICROCHIP [Microchip Technology]

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TC7116/A/TC7117/A

DS21457B-page 10

FIGURE 3-5:

TC7116/TC7116A DIGITAL SECTION

3.2.1

SYSTEM TIMING

Theclockingmethodusedfor theTC7116/TC7116A

and TC7117/TC7117A is shown in Figure 3-6. Three

clocking methods may be used:

1.

An external oscillator connected to Pin 40.

2.

A crystal between Pins 39 and 40.

3.

An RC network using all three pins.

The oscillator frequency is

÷4 before it clocks the

decade counters. It is then further divided to form the

three convert cycle phases: Signal Integrate (1000

counts), Reference De-integrate (0 to 2000 counts),

and Auto-Zero (1000 to 3000 counts). For signals less

than full scale, auto-zero gets the unused portion of ref-

erence de-integrate. This makes a complete measure

cycle of 4000 (16,000 clock pulses), independent of

input voltage. For 3 readings per second, an oscillator

frequency of 48kHz would be used.

To achieve maximum rejection of 60Hz pickup, the sig-

nal integrate cycle should be a multiple of 60Hz. Oscil-

lator frequencies of 240kHz, 120kHz, 80kHz, 60kHz,

48kHz, 40kHz, etc. should be selected. For 50Hz rejec-

tion,

oscillator

frequencies

of

200kHz,

100kHz,

66-2/3kHz, 50kHz, 40kHz, etc. would be suitable. Note

that 40kHz (2.5 readings per second) will reject both

50Hz and 60Hz.

3.2.2

HOLD READING INPUT

When HLDR is at a logic HIGH, the latch will not be

updated. Analog-to-digital conversions will continue,

but will not be updated until HLDR is returned to LOW.

To continuously update the display, connect to TEST

(TC7116/TC7116A) or GROUND (TC7117/TC7117A),

or disconnect. This input is CMOS compatible with

70k

Ω typical resistance to TEST (TC7116/TC7116A) or

GROUND (TC7117/TC7117A).

TC7116

TC7116A

LCD Phase Driver

Thousands

Hundreds

Tens

Units

4

Backplane

21

39

37

OSC2

Internal Digital Ground

V+

V-

TEST

6.2V

500

Ω

26

35

To Switch Drivers

From Comparator Output

Clock

VTH = 1V

7-Segment

Decode

7-Segment

Decode

7-Segment

Decode

200

40

38

Typical Segment Output

Internal Digital Ground

Segment

Output

V+

0.5mA

2mA

Latch

OSC3

OSC1

÷

HLDR

~70k

Ω

Logic Control

1

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