LM2657

SNVS342B – JANUARY 2005 – REVISED MARCH 2013

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PIN DESCRIPTION (continued)

Pin 14,

Output voltage sense pin for Channel 2. See Pin 1.

SENSE2:

Pin 15, ILIM2:

Channel 2 Current Limit pin. When the bottom FET is ON, a 62µA (typical) current flows out of this pin into an external

current limit setting resistor connected to the drain of the lower FET. This is a current source so the drop across this

resistor tries to push the voltage on this pin to a more positive value. However, the drain of the lower FET, which is

connected to the other side of the same resistor, is trying to go more negative as the load current increases. Therefore at

some value of current, the voltage on this pin will cross zero and start to go negative. This is the current limiting condition

and it is detected by the ‘Current Limit Comparator’ seen in the BLOCK DIAGRAM. When a current limit condition has

been detected, the next ON-pulse of the upper FET will be omitted. The lower FET will again be monitored to determine if

the current has fallen below the threshold. If it has, the next ON-pulse will be permitted. If not, the upper FET will stay

OFF, and remain so for several cycles if necessary, until the current returns to normal. Eventually, if the overcurrent

condition persists and the upper FET has not been turned ON, the output will start to fall eventually triggering “Power not

Good”.

Pin 16, SW2:

The Switching node of the buck regulator of Channel 2. Also serves as the lower rail of the floating driver of the upper

FET.

Pin 17, HDRV2: Gate drive pin for the upper FET of Channel 2 (High-side drive). The top gate driver is interlocked with the bottom gate

driver to prevent shoot-through/cross-conduction.

Pin 18, BOOT2: Bootstrap pin for Channel 2. This is the upper supply rail for the floating driver of the upper FET. It is bootstrapped by

means of a ceramic capacitor connected to the channel Switching node. This capacitor is charged up by the IC to a value

of about 5V as derived from the V5 pin (Pin 21).

Pin 19, PGND2: Power Ground pin of Channel 2. This is the return path for the bottom FET gate drive. Both the PGND's are to be

connected on the PCB to the system ground and also to the Signal ground (Pin 7) in accordance with the recommended

Layout Guidelines .

Pin 20, LDRV2:

Gate drive pin for the Channel 2 bottom FET (Low-side drive). The bottom gate driver is interlocked with the top gate

driver to prevent shoot-through/cross-conduction.

Pin 21, V5:

Upper rail of the lower FET drivers of both channels. Also used to charge up the bootstrap capacitors of the upper FET

drivers. This is connected to an external 5V supply. The 5V rail may be the same as the rail used to provide power to the

VDD pin (Pin 5). If these rails are connected, the VDD pin must be well-decoupled so that it does not interact with the V5

pin. A minimum 0.1µF (ceramic) capacitor should be placed on the component side very close to the IC with no

intervening vias between this capacitor and the V5/PGND pins.

Pin 22, VIN:

The input that powers both the buck regulator channels. It also is used by the internal ramp generator to implement the

line ‘feedforward’ feature. The VIN pin is also used with the SENSE pin voltage to predict the CCM (continuous

conduction mode) duty cycle and to thereby set the minimum allowed DCM duty cycle to 85% of the CCM value (in SKIP

mode, see Pin 10). This is a high input impedance pin, drawing only about 115µA from the input rail. A fault condition will

occur if this voltage drops below its UVLO threshold.

Pin 23, LDRV1:

LDRV pin of Channel 1. See Pin 20.

Pin 24, PGND1: PGND pin for Channel 1.See Pin 19.

Pin 25, BOOT1: Boot pin of Channel 1. See Pin 18.

Pin 26, HDRV1: HDRV pin of Channel 1. See Pin 17.

Pin 27, SW1:

SW pin of Channel 1. See Pin 16.

Pin 28, ILIM1:

Channel 1 Current Limit pin. See Pin 15.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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