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ISL29038IROZ-EVALZ Fiches technique(PDF) 4 Page - Intersil Corporation |
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ISL29038IROZ-EVALZ Fiches technique(HTML) 4 Page - Intersil Corporation |
4 / 15 page ISL29038 4 FN7851.1 January 23, 2015 Submit Document Feedback ProxWASH Washout Bit Activation Level Norwood Solar Emulator 40k Lux ProxOffsetMax Maximum PROX Offset, Referenced to Proximity ADC Range 512 LSB ProxOffsetInc Proximity Offset Adjust Increment Referenced to Proximity ADC Range 27 LSB LED DRIVER (IRDR PIN) tr Rise Time for IRDR Sink Current RLOAD = 15Ω at IRDR pin, 20% to 80% 25 ns tf Fall time for IRDR Sink Current RLOAD = 15Ω at IRDR pin, 80% to 20% 15 ns IIRDR_0 IRDR Sink Current PROX_DR = 0; VIRDR = 0.5V 31.25 mA IIRDR_1 IRDR Sink Current PROX_DR = 1; VIRDR = 0.5V 62.5 mA IIRDR_2 IRDR Sink Current PROX_DR = 2; VIRDR = 0.5V 125 mA IIRDR_3 IRDR Sink Current PROX_DR = 3; VIRDR = 0.5V 250 mA IIRDR_LEAK IRDR Leakage Current PROX_EN = 0; VIRDR = 3.63V 0.001 1 µA VIRDR IRDR Pin Voltage Compliance Register bit PROX_DR = 0 0.50 4.3 V tPULSE IIRDR On Time Per PROX Reading 90 µs MISCELLANEOUS VREF Voltage of REXT Pin ALS_EN = 1 or PROX_EN = 1 0.52 V Electrical Specifications VDD = 3.0V, TA = +25°C, REXT = 499kΩ 1% tolerance. (Continued) PARAMETER DESCRIPTION TEST CONDITION MIN (Note 7)TYP MAX (Note 7)UNITS I2C Electrical Specifications For SCL and SDA unless otherwise noted, VDD = 3V, TA = +25°C, REXT = 499kΩ 1% tolerance (Note 11). SYMBOL PARAMETER TEST CONDITIONS MIN (Note 7) TYP MAX (Note 7) UNITS VI2C Supply Voltage Range for I2C Interface 1.7 3.63 V fSCL SCL Clock Frequency 400 kHz VIL SCL and SDA Input Low Voltage 0.55 V VIH SCL and SDA Input High Voltage 1.25 V Vhys Hysteresis of Schmitt Trigger Input 0.05VDD V VOL Low-level Output Voltage (open-drain) at 4mA Sink Current 0.4 V Ii Input Leakage for each SDA, SCL Pin -10 10 µA tSP Pulse Width of Spikes that must be Suppressed by the Input Filter 50 ns tAA SCL Falling Edge to SDA Output Data Valid 900 ns Ci Capacitance for each SDA and SCL Pin 10 pF tHD:STA Hold Time START Condition After this period, the first clock pulse is generated 600 ns tLOW LOW Period of the SCL Clock Measured at the 30% of VDD crossing 1300 ns tHIGH HIGH Period of the SCL Clock 600 ns tSU:STA Set-up Time for a START Condition 600 ns tHD:DAT Data Hold Time 30 ns tSU:DAT Data Set-up Time 100 ns |
Numéro de pièce similaire - ISL29038IROZ-EVALZ |
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Description similaire - ISL29038IROZ-EVALZ |
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