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ISL267452IHZ-T Fiches technique(PDF) 10 Page - Intersil Corporation |
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ISL267452IHZ-T Fiches technique(HTML) 10 Page - Intersil Corporation |
10 / 16 page ISL267452 10 FN8255.0 July 26, 2012 Functional Description The ISL267452 is based on a successive approximation register (SAR) architecture utilizing capacitive charge redistribution digital to analog converters (DACs). Figure 19 shows a simplified representation of the converter. During the acquisition phase (ACQ) the differential input is stored on the sampling capacitors (CS). The comparator is in a balanced state since the switch across its inputs is closed. The signal is fully acquired after tACQ has elapsed, and the switches then transition to the conversion phase (CONV) so the stored voltage may be converted to digital format. The comparator will become unbalanced when the differential switch opens and the input switches transition (assuming that the stored voltage is not exactly at mid-scale). The comparator output reflects whether the stored voltage is above or below mid-scale, which sets the value of the MSB. The SAR logic then forces the capacitive DACs to adjust up or down by one quarter of full-scale by switching in binarily weighted capacitors. Again, the comparator output reflects whether the stored voltage is above or below the new value, setting the value of the next lowest bit. This process repeats until all 12 bits have been resolved. An external clock must be applied to the SCLK pin to generate a conversion result. The allowable frequency range for SCLK is 10kHz to 10MHz (555kSPS). Serial output data is transmitted on the falling edge of SCLK. The receiving device (FPGA, DSP or Microcontroller) may latch the data on the rising edge of SCLK to maximize set-up and hold times. A stable, low-noise reference voltage must be applied to the VREF pin to set the full-scale input range and common-mode voltage. See “Voltage Reference Input” on page 11 for more details. ADC Transfer Function The output coding for the ISL267452 is twos complement. The first code transition occurs at successive LSB values (i.e., 1 LSB, 2 LSB, and so on). The LSB size of the ISL267452 is 2*VREF/4096. The ideal transfer characteristic of the ISL267452 is shown in Figure 20. FIGURE 17. CHANGE IN ENOB vs REFERENCE VOLTAGE FOR VDD = 5V AND 3V FOR THE ISL267452 FIGURE 18. HISTOGRAM OF 10,000 CONVERSIONS OF A DC INPUT FOR THE ISL267452 WITH VDD = 5V Typical Performance Characteristics (Continued) 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VREF (V) 5V 3V 0 10k 20k 30k 40k 50k 60k 70k 2044 2045 2046 2047 2048 2049 2050 CODE 65,516 CODES 10 CODES 10 CODES FIGURE 19. SAR ADC ARCHITECTURAL BLOCK DIAGRAM VIN + VIN – VREF ACQ CONV ACQ ACQ CONV CONV SAR LOGIC CS CS FIGURE 20. IDEAL TRANSFER CHARACTERISTICS 1LSB = 2•VREF/4096 100...000 100...001 100...010 111...111 000...000 000...001 011...110 011...111 ANALOG INPUT VIN+ – (VIN–) –VREF + ½LSB +VREF – 1½LSB 0V +VREF – 1LSB |
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