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ISL26712IRTZ-T7A Fiches technique(PDF) 7 Page - Intersil Corporation

No de pièce ISL26712IRTZ-T7A
Description  12-Bit, 10-Bit and 8-Bit, 1MSPS SAR ADCs
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Fabricant  INTERSIL [Intersil Corporation]
Site Internet  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL26712IRTZ-T7A Fiches technique(HTML) 7 Page - Intersil Corporation

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ISL26712, ISL26710, ISL26708
7
FN7999.3
September 5, 2012
IDD
Positive Supply Input Current
Static
11
1
µA
Dynamic
3V
1250
1250
1250
µA
5V
1700
1700
1700
µA
Power Dissipation
Static Mode
VDD = 3V
333
µW
VDD = 5V
555
µW
Dynamic
VDD = 3V, fsmpl =1MSPS
3.75
3.75
3.75
mW
VDD = 5V, fsmpl =1MSPS
8.50
8.50
8.50
mW
NOTES:
10. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
11. The absolute voltage applied to each analog input must be between GND and VDD to guarantee datasheet performance.
Electrical Specifications VDD = +3.0V to +3.6V, FSCLK = 18MHz, FS = 1MSPS, VREF = 2.0V; VDD = +4.75V to +5.25V, FSCLK = 18MHz,
FS =1MSPS, VREF = 2.5V; VCM = VREF, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature
range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
ISL26712
ISL26710
ISL26708
UNITS
MIN
(Note 10)
TYP
MAX
(Note 10)
MIN
(Note 10)
TYP
MAX
(Note 10)
MIN
(Note 10)
TYP
MAX
(Note 10)
Timing Specifications
VDD = 3.0V to 3.6V, fSCLK = 18MHz, fS = 1MSPS, VREF = 2.0V; VDD = 4.75V to 5.25V, fSCLK =18MHz,
fS =1MSPS, VREF =2.5V; VCM = VREF unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
(Note 12)
TEST CONDITIONS
MIN
(Note 10)
TYP
MAX
(Note 10)
UNITS
fSCLK
Clock Frequency
0.01
18
MHz
tSCLK
Clock Period
55
ns
tACQ
Acquisition Time (Note 13)
ns
tCONV
Conversion Time
888
ns
tCSW
CS Pulse Width
10
ns
tCSS
CS Falling Edge to SCLK Falling Edge Setup Time
10
ns
tCDV
CS Falling Edge to SDATA Valid
20
ns
tCLKDV
SCLK Falling Edge to SDATA Valid
40
ns
tSDH
SCLK Falling Edge to SDATA Hold
10
ns
tSW
SCLK Pulse Width
0.4 x tSCLK
0.6 x tSCLK
ns
tDISABLE
CSB Rising Edge to SDATA Disable Time
(Note 14)
Extrapolated back to true bus relinquish
10
35
ns
tQUIET
Quiet Time Before Sample
60
ns
NOTES:
12. Limits established by characterization and are not production tested.
13. See “ACQUISITION TIME” on page 17.
14. During characterization, tDISABLE is measured from the release point with a 10pF load (see Figure 4).


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