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ESD5V5U5ULC Fiches technique(PDF) 4 Page - Infineon Technologies AG |
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ESD5V5U5ULC Fiches technique(HTML) 4 Page - Infineon Technologies AG |
4 / 16 page ESD5V5U5ULC Ultra-low Capacitance ESD / Transient / Surge Protection Array Final Data Sheet 4 Revision 1.3, 2015-07-16 1 Ultra-low Capacitance ESD / Transient / Surge Protection Array 1.1 Features • ESD / Transient protection of high speed data lines exceeding – IEC61000-4-2 (ESD): ±25 kV (air / contact) – IEC61000-4-4 (EFT): ±2.5 kV / ±50 A (5/50 ns) – IEC61000-4-5 (surge): ±6 A (8/20 μs) • Maximum working voltage: VRWM = 5.5 V • Extremely low capacitance CL = 0.45 pF I/O to GND (typical) • Very low dynamic resistance: RDYN I/O to GND = 0.2 Ω (typical) • Very low reverse clamping voltage: VCL = 9 V (typical) at IPP = 16 A • Protection of VBUS with one line freely selectable • Pb-free (RoHS compliant) package 1.2 Application Examples • Protection of all I/O and VBUS lines in dual USB2.0 ports • 10/100/100 Ethernet • DVI, HDM, FireWire 1.3 Product Description Figure 1 Pin Configuration and Schematic Diagram Table 1 Ordering Information Type Package Configuration Marking code ESD5V5U5ULC SC74 5 lines, uni-directional 20 ESD5V5U5ULC_PinConf_and_SchematicDiag.vsd SC74 Pin 2 Pin 3 Pin 6Pin 5Pin 4 Pin 1 a) Pin configuration b) Schematic diagram Pin 5 Pin 1 Pin 3 Pin 4 Pin 2 GND Pin 6 |
Numéro de pièce similaire - ESD5V5U5ULC_15 |
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Description similaire - ESD5V5U5ULC_15 |
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