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STC3800 Fiches technique(PDF) 11 Page - Connor-Winfield Corporation |
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STC3800 Fiches technique(HTML) 11 Page - Connor-Winfield Corporation |
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11 / 48 page  Preliminary Data Sheet #: TM061 Page 11 of 48 Rev: P06 Date: 11/22/04 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Detailed Description continued In slave mode, the operational mode is “locked” and the reference is the Xref input. See Register Descriptions and Operation and Application section: Control Modes for more details. The VC_Sel pin determines if the VCXO input to the chip is TTL or PECL, 1 = TTL, 0 = PECL. See Application Notes, Peripherals section. Following any device reset, either via power-up or operation of the Reset pin, the device needs to be loaded with its DPLL configuration data. This data may come from either an external EEPROM, or the bus interface. The Dmode pin selects the source for configuration data, 0 = from the bus interface, 1 = from the EEPROM. If the source is an EEPROM, devices pre-loaded with the configuration data are available from Connor-Winfield (See Application Notes, External Component Selection section). Data may also be loaded into or read from the EEPROM via the bus interface (See Application Notes, Reading and Writing EEPROM Data section). If the data is to be application provided on reset through the bus interface (i.e. the optional EEPROM is not equipped), the data is available from Connor-Winfield as a file and is loaded per the procedure described in the Application Note, Configuration Data section. Control Modes Parallel or serial bus interfaces are provided to access STC3800 internal control and status registers.The selected reference, operational modes can be accessed from either the bus interface or external device pins. Master/slave mode can only be controlled by M/S pin. Hardware Control – The device may be configured for direct pin control over key functions for simple hardwired configurations. The HM_Ref pin enables hardware control of reference selection and operational mode. When it is a “1”, mode control and reference input selection may be provided by direct hardware pin inputs Sel0-3 (see Table 5) and the corresponding register access becomes read-only. When HM_Ref is disabled (=0), reference selection and operational mode control is via register access. The M/S pin determines master or slave mode. 1=Master, 0=Slave. In master mode and with HM_Ref = 1, the hardware control of operational mode and reference selection are as shown in the table below: Hardware Reference Selection and Mode Control Table 5 Pin Function Sel3 Sel2 Sel1 Sel0 Mode Reference 0 0 0 0 Free Run N/A 0 0 0 1 Locked 1 0 0 1 0 Locked 2 0 0 1 1 Locked 3 0 1 0 0 Locked 4 0 1 0 1 Locked 5 0 1 1 0 Locked 6 0 1 1 1 Locked 7 1 0 0 0 Locked 8 1 0 0 1 Hold Over N/A 1 0 1 0 Hold Over N/A 1 0 1 1 Hold Over N/A 1 1 0 0 Hold Over N/A 1 1 0 1 Hold Over N/A 1 1 1 0 Hold Over N/A 1 1 1 1 Hold Over N/A |
Numéro de pièce similaire - STC3800_15 |
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Description similaire - STC3800_15 |
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