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74LVT573 Fiches technique(PDF) 8 Page - NXP Semiconductors |
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74LVT573 Fiches technique(HTML) 8 Page - NXP Semiconductors |
8 / 17 page 74LVT573 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 8 — 22 November 2011 8 of 17 NXP Semiconductors 74LVT573 3.3 V octal D-type transparent latch; 3-state 11. Waveforms Measurement points are given in Table 8. Measurement points are given in Table 8. Fig 6. Propagation delays latch enable input (LE) to output (Qn), and latch enable (LE) pulse width Fig 7. Propagation delay data input (Dn) to output (Qn) Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Measurement points are given in Table 8. Fig 8. Output enable time to HIGH-state and output disable time from HIGH-state Fig 9. Output enable time to LOW-state and output disable time from LOW-state Measurement points are given in Table 8. Remark: The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 10. Data setup and hold times for data (Dn) and latch enable (LE) inputs 001aai743 LE input Qn output tPHL tPLH tWH VM VOH VI 0 V VOL VM tWL 001aai742 Dn input Qn output tPHL tPLH 0 V VI VM VM VOH VOL Qn output 001aai745 OE input VM VI VOH 0 V 0 V tPZH tPHZ VY VM VM 001aai746 tPZL tPLZ VM VM VM Qn output OE input VI VOL 3.0 V VX 0 V 001aai744 th(L) tsu(L) th(H) tsu(H) VM VM VI 0 V VI 0 V LE input Dn input Table 8. Measurement points Input Output VM VM VX VY 1.5V 1.5V VOL + 0.3 V VOH 0.3 V |
Numéro de pièce similaire - 74LVT573_15 |
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Description similaire - 74LVT573_15 |
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