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Moteur de recherche de fiches techniques de composants électroniques |
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9ZXL1530 Fiches technique(PDF) 8 Page - Integrated Device Technology |
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9ZXL1530 Fiches technique(HTML) 8 Page - Integrated Device Technology |
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8 / 19 page  9ZXL1530 15-OUTPUT LOW POWER DIFFERENTIAL ZBUFFER FOR PCIE GEN3 AND QPI IDT® 15-OUTPUT LOW POWER DIFFERENTIAL ZBUFFER FOR PCIE GEN3 AND QPI 8 9ZXL1530 REV C 031312 Electrical Characteristics–Skew and Differential Jitter Parameters TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES CLK_IN, DIF[x:0] tSPO_PLL Input-to-Output Skew in PLL mode nominal value @ 25°C, 3.3V -100 -44 100 ps 1,2,4,5,8 CLK_IN, DIF[x:0] tPD_BYP Input-to-Output Skew in Bypass mode nominal value @ 25°C, 3.3V 2.5 3.6 4.5 ns 1,2,3,5,8 CLK_IN, DIF[x:0] tDSPO_PLL Input-to-Output Skew Varation in PLL mode across voltage and temperature -50 -2 50 ps 1,2,3,5,8 CLK_IN, DIF[x:0] tDSPO_BYP Input-to-Output Skew Varation in Bypass mode across temperature for a given voltage -250 250 ps 1,2,3,5,8 CLK_IN, DIF[x:0] tDTE Random Differential Tracking error beween two 9ZX devices in Hi BW Mode 35 ps (rms) 1,2,3,5,8 CLK_IN, DIF[x:0] tDSSTE Random Differential Spread Spectrum Tracking error beween two 9ZX devices in Hi BW Mode 15 75 ps 1,2,3,5,8 DIF{x:0] tSKEW_ALL Output-to-Output Skew across all outputs (Common to Bypass and PLL mode) 45 65 ps 1,2,3,8 PLL Jitter Peaking jpeak-hibw LOBW#_BYPASS_HIBW = 1 0 1.75 2.5 dB 7,8 PLL Jitter Peaking jpeak-lobw LOBW#_BYPASS_HIBW = 0 0 0.75 2 dB 7,8 PLL Bandwidth pllHIBW LOBW#_BYPASS_HIBW = 1 2 3.33 4 MHz 8,9 PLL Bandwidth pllLOBW LOBW#_BYPASS_HIBW = 0 0.7 1.18 1.4 MHz 8,9 Duty Cycle tDC Measured differentially, PLL Mode 45 50.4% 55 % 1 Duty Cycle Distortion tDCD Measured differentially, Bypass Mode @100MHz -2 0 2 % 1,10 PLL mode 24 50 ps 1,11 Additive Jitter in Bypass Mode 0 50 ps 1,11 Notes for preceding table: 6.t is the period of the input clock 7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking. 8. Guaranteed by design and characterization, not 100% tested in production. 9 Measured at 3 db down or half power point. 10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. 11 Measured from differential waveform 3 All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it. 4 This parameter is deterministic for a given device 5 Measured with scope averaging on to find mean value. Jitter, Cycle to cycle tjcyc-cyc 1 Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input. 2 Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present. |
Numéro de pièce similaire - 9ZXL1530 |
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Description similaire - 9ZXL1530 |
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