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MAX3270 Datasheet(Fiches technique) 6 Page - Maxim Integrated Products

Numéro de pièce MAX3270
Description  155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector
Télécharger  12 Pages
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Fabricant  MAXIM [Maxim Integrated Products]
Site Internet  http://www.maxim-ic.com
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 6 page
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155Mbps/622Mbps Clock Recovery and
Data Retiming IC with Fully Integrated
Phase/Frequency Detector
6
_______________________________________________________________________________________
______________________________________________________________Pin Description
Loop Filter Positive. This pin connects to an external filter.
FILP
9
Loop Filter Negative. This pin connects to an external filter.
FILN
10
TTL Positive Supply: +5.0V
VTTL
11
Negative Supply for VCO: -4.5V
AVEE2
12
External Clock-Select TTL Input. A logical high selects the external clock.
EXCS
13
Ground for Input Buffers: 0V
AVCC
5
Frequency Monitor Output. This pin monitors the input voltage to the VCO. When the PLL is locked,
the pin will be
≅ 0V.
FM
6
Guard-Ring Positive Supply to Epi: 0V
AVCC
7
Loop Filter Ground. This pin connects to an external filter.
FILG
8
Serial Data Input: 155Mbps or 622Mbps. Differential ECL Negative.
SDIN
4
Serial Data Input: 155Mbps or 622Mbps. Differential ECL Positive.
SDIP
3
PIN
Negative Supply for Input Buffers: -4.5V
AVEE1
2
Guard-Ring Negative Supply to Substrate: -4.5V
GVEE
1
FUNCTION
NAME
14
EXC
External Clock. Single-ended ECL input.
15, 16
AVCC
Ground for VCO: 0V
17, 19, 38,
39
DVCC
Digital Ground for Mux: 0V
18
CRS
Clock-Rate Select TTL Input. This selects the clock rate to be either 155Mbps or 622Mbps. A logic-
high level selects the 622Mbps mode.
20
RST
Resets all digital flip-flops, TTL input. Reset is assert when low.
21, 22, 34,
35, 36
DVEE
Digital Negative Supply: -4.5V
23, 33, 37,
40, 43, 44
N.C.
No Connection
24, 27, 29,
32
OVCC
Output Driver Ground: 0V
25
RDON
Negative Recovered Data Output, differential ECL output: 155Mbps or 622Mbps.
26
RDOP
Positive Recovered Data Output, differential ECL output: 155Mbps or 622Mbps.
28
CRP
Clock-Reference Output Divide-by-4. ECL low-power single-ended: 38Mbps or 155Mbps.
30
RCON
Negative Recovered Clock Output, differential ECL output: 155Mbps or 622Mbps.
31
RCOP
Positive Recovered Clock Output, differential ECL output: 155Mbps or 622Mbps.
41
PHADJ
Phase Adjust. This is an analog adjustment that varies the static phase between the input data and
the recovered clock. If not used, this input should be grounded. The range is from -1V to 1V.
42
VR
Phase Reference Voltage: 0V. The PHADJ pin compares to this voltage. Set to ground.




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